STV3550 Datasheet, PDF (108/144 Pages) STMicroelectronics – LCD and Matrix Display TV Processor

STV3550
3. In slave mode (and in multi-master configurations), it is necessary to determine if the first byte
received after a START condition is the address of the SSC2. If it is, then an acknowledge
must be generated in the 9th bit position.
Subsequently, an interrupt must be generated to inform the software that the SSC2 has been
addressed as a slave device and therefore that it needs to either send data to the addressing
master or to receive data from it.
In addition to normal 7 bit addressing, there is an extended 10 bit addressing mode where the
address is spread over 2 bytes. So in this mode, the SSC2 must compare 2 consecutive bytes
with the incoming data after a START condition. It must also generate acknowledge bits for the
first and second bytes automatically if the address matches.
The 10 bit addressing mode is further complicated by the fact that if the slave has been
previously addressed for writing with the full 2 byte address, then the master can issue a
repeated START condition and then transmit just the first address byte for a read. The slave
therefore must remember that it has already been addressed and must respond.
4. In order for the software interrupt handler to have time to service interrupts, the SSC2 can hold
the clock line LOW until the software releases it. This is called clock stretching.
5. In master mode, the SSC2 must begin a transmission by generating a START condition and
must end transmission by generating a STOP condition. In multi-master configurations a
START condition should not be generated if the bus is already busy (i.e. a START condition
has already been received).
6. When the SSC2 is receiving data from another device, it must generate acknowledge bits in
the 9th bit position. However, when receiving data as a master the last byte received must NOT
be acknowledged. This only applies to data bytes; when operating as a slave device, the SSC2
should always acknowledge a matching address byte (i.e. the first byte after a START
condition).
7. In multi-master configurations, arbitration must take place because it is not possible to
determine if another master is also trying to transmit to the bus (i.e. the START conditions were
generated within the allowed time frame).
Arbitration involves checking that the data being transmitted is the same as the data received.
If this is not the case, then we have lost arbitration. The SSC2 must then continue to transmit a
HIGH logic level for the rest of the byte to avoid corrupting the bus.
It is also possible that, having lost arbitration, we are being addressed as a slave device. So
the SSC2 must then go into slave mode and compare the address in the normal fashion (and
generate an acknowledge if we are addressed).
After the byte plus acknowledge the SSC2 must indicate to the software that we have lost
arbitration by setting a flag.
All of these features are provided in the SSC2 design. They are controlled by the I²C control block
which interacts with various other modules to perform the protocols.
In order to program for I²C mode, a separate control register is provided, SSCI2C.
To perform any of the I²C hardware features, the I²C control enable bit, SSCI2CM, must be set.
When the I²C control bit is set, the clock synchronization mechanism is always enabled (see
Section 7.7.18: Clock Synchronization).
When the I²C control bit is set the START and STOP condition detection is performed.
To program the slave address of the SSC2 the slave address register, SSCSLAD must be written to
with the address value. In the case of 7 bit addresses, only 7 bits should be written. For 10 bit
addressing, the full 10 bits are written to. The SSC2 then uses this register to compare the slave
address transmitted after a START condition (see Section 7.7.20: Slave Address Comparison).
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