STM32F215RGT6 Datasheet, PDF (107/173 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

STM32F21xxx
Electrical characteristics
Table 52. I²S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
f_CK
1/t_c(CK)
I²S clock frequency
t_r(CK)
t_f(CK)
t_v(WS) ⁽³⁾
t_h(WS) ⁽³⁾
t_su(WS) ⁽³⁾
t_h(WS) ⁽³⁾
t_w(CKH) ⁽³⁾
t_w(CKL) ⁽³⁾
t_{su(SD_MR)} ⁽³⁾
t_{su(SD_SR)} ⁽³⁾
t_{h(SD_MR)(3)(4)}
t_{h(SD_SR)} ⁽³⁾⁽⁴⁾
I²S clock rise and fall time
WS valid time
WS hold time
WS setup time
WS hold time
CK high and low time
Data input setup time
Data input hold time
t_{v(SD_ST)} ⁽³⁾⁽⁴⁾ Data output valid time
Master, 16-bit data,
audio frequency = 48 kHz, main
clock disabled
Slave
capacitive load C_L = 50 pF
Master
Master
Slave
Slave
Master f_PCLK= 30 MHz
Master receiver
Slave receiver
Master receiver: f_PCLK= 30 MHz,
Slave receiver: f_PCLK= 30 MHz
Slave transmitter (after enable
edge)
1.23
0
-
0.3
0
3
0
396
45
0
13
0
-
1.24
64F_S(1)
(2)
MHz
-
-
-
-
-
-
ns
-
30
t_{h(SD_ST)} ⁽³⁾
Data output hold time
Slave transmitter (after enable
edge)
10
-
t_{v(SD_MT)} ⁽³⁾⁽⁴⁾ Data output valid time
Master transmitter (after enable
edge)
-
6
t_{h(SD_MT)} ⁽³⁾ Data output hold time
Master transmitter (after enable
edge)
0
-
1. F_S is the sampling frequency. Refer to the I2S section of the STM32F20xxx/21xxx reference manual for more details. f_CK
values reflect only the digital peripheral behavior which leads to a minimum of (I2SDIV/(2*I2SDIV+ODD), a maximum of
(I2SDIV+ODD)/(2*I2SDIV+ODD) and F_S maximum values for each mode/condition.
2. Refer to Table 45: I/O AC characteristics.
3. Based on design simulation and/or characterization results, not tested in production.
4. Depends on f_PCLK. For example, if f_PCLK=8 MHz, then T_PCLK = 1/f_PLCLK =125 ns.
Doc ID 17050 Rev 8
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