STM32F215RGT6 Datasheet, PDF (104/173 Pages) STMicroelectronics – ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM

Electrical characteristics
STM32F21xxx
I²S - SPI interface characteristics
Unless otherwise specified, the parameters given in Table 51 for SPI or in Table 52 for I²S
are derived from tests performed under the ambient temperature, f_PCLKx frequency and V_DD
supply voltage conditions summarized in Table 11.
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I²S).
Table 51. SPI characteristics
Symbol
Parameter
Conditions
Min
Max Unit
f_SCK
1/t_c(SCK)
SPI clock frequency
SPI1 master/slave mode
SPI2/SPI3 master/slave mode
-
30
MHz
-
15
t_r(SCL)
t_f(SCL)
SPI clock rise and fall ^{Capacitive load: C = 30 pF,}
time
f_PCLK = 30 MHz
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
t_su(NSS)(1)
t_h(NSS)(1)
t_w(SCLH)(1)
t_w(SCLL)(1)
NSS setup time
Slave mode
NSS hold time
Slave mode
SCK high and low time
Master mode, f_PCLK = 30 MHz,
presc = 2
t_su(MI) ⁽¹⁾
t_su(SI)(1)
Master mode
Data input setup time
Slave mode
-
8
ns
30
70
%
4t_PCLK
-
2t_PCLK
-
t_PCLK-3 t_PCLK+3
5
-
5
-
t_h(MI) ⁽¹⁾
t_h(SI)(1)
Data input hold time
t_a(SO)(1)(2)
Data output access
time
Master mode
Slave mode
Slave mode, f_PCLK = 30 MHz
5
-
4
-
ns
0
3t_PCLK
t_{dis(SO)(1)(3)}
Data output disable
time
Slave mode
2
10
t_v(SO) ⁽¹⁾ Data output valid time Slave mode (after enable edge)
-
25
t_v(MO)(1) Data output valid time Master mode (after enable edge)
-
5
t_h(SO)(1)
Slave mode (after enable edge)
15
-
Data output hold time
t_h(MO)(1)
Master mode (after enable edge)
2
-
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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Doc ID 17050 Rev 8