STM32F401XD Datasheet, PDF (103/135 Pages) STMicroelectronics – Clock, reset and supply management

STM32F401xD STM32F401xE
Electrical characteristics
I²S interface characteristics
Unless otherwise specified, the parameters given in Table 62 for the I²S interface are
derived from tests performed under the ambient temperature, f_PCLKx frequency and V_DD
supply voltage conditions summarized in Table 14, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V_DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (CK, SD, WS).
Table 62. I²S dynamic characteristics⁽¹⁾
Symbol
Parameter
Conditions
Min
f_MCK
f_CK
I2S Main clock output
I2S clock frequency
-
Master data: 32 bits
Slave data: 32 bits
D_CK I2S clock frequency duty cycle Slave receiver
t_v(WS)
WS valid time
Master mode
t_h(WS)
WS hold time
Master mode
t_su(WS)
WS setup time
Slave mode
t_h(WS)
WS hold time
Slave mode
t_{su(SD_MR)}
t_{su(SD_SR)}
Data input setup time
Master receiver
Slave receiver
t_{h(SD_MR)}
t_{h(SD_SR)}
Data input hold time
Master receiver
Slave receiver
t_{v(SD_ST)}
t_{h(SD_ST)}
Data output valid time
Slave transmitter (after enable edge)
t_{v(SD_MT)}
Master transmitter (after enable edge)
t_{h(SD_MT)}
Data output hold time
Master transmitter (after enable edge)
1. Guaranteed by characterization, not tested in production.
2. The maximum value of 256xFs is 42 MHz (APB1 maximum frequency).
256x8K
-
-
30
0
0
1
0
7.5
2
0
0
-
-
2.5
Max
256xFs⁽²⁾
64xFs
64xFs
70
6
-
-
-
-
-
-
-
27
20
-
Unit
MHz
MHz
%
ns
Note:
Refer to the I2S section of the reference manual for more details on the sampling frequency
(F_S).
f_MCK, f_CK, and D_CK values reflect only the digital peripheral behavior. The values of these
parameters might be slightly impacted by the source clock precision. D_CK depends mainly
on the value of ODD bit. The digital contribution leads to a minimum value of
(I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). F_S
maximum value is supported for each mode/condition.
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