STM32F401XD Datasheet, PDF (100/135 Pages) STMicroelectronics – Clock, reset and supply management

Electrical characteristics
STM32F401xD STM32F401xE
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 61 for the SPI interface are
derived from tests performed under the ambient temperature, f_PCLKx frequency and V_DD
supply voltage conditions summarized in Table 14, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 10
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5V_DD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 61. SPI dynamic characteristics⁽¹⁾
Symbol
Parameter
Conditions
Min
Typ
Max Unit
f_SCK
1/t_c(SCK)
Duty(SCK)
SPI clock frequency
Duty cycle of SPI clock
frequency
Master mode, SPI1/4,
2.7 V < V_DD < 3.6 V
Slave mode, SPI1/4,
2.7 V < V_DD < 3.6 V
Slave transmitter/full-duplex mode,
SPI1/4, 2.7 V < V_DD < 3.6 V
Master mode, SPI1/2/3/4,
1.7 V < V_DD < 3.6 V
Slave mode, SPI1/2/3/4,
1.7 V < V_DD < 3.6 V
Slave mode
t_w(SCKH)
t_w(SCKL)
t_su(NSS)
t_h(NSS)
t_su(MI)
t_su(SI)
t_h(MI)
t_h(SI)
t_a(SO)
t_dis(SO)
t_v(SO)
t_h(SO)
SCK high and low time Master mode, SPI presc = 2
NSS setup time
Slave mode, SPI presc = 2
NSS hold time
Slave mode, SPI presc = 2
Master mode
Data input setup time
Slave mode
Data input hold time
Master mode
Slave mode
Data output access time Slave mode
Data output disable time Slave mode
Data output valid time
Data output hold time
Slave mode (after enable edge),
2.7 V < V_DD < 3.6 V
Slave mode (after enable edge),
1.7 V < V_DD < 3.6 V
Slave mode (after enable edge),
2.7 V < V_DD < 3.6 V
Slave mode (after enable edge),
1.7 V < V_DD < 3.6 V
42
42
-
-
38⁽²⁾ MHz
21
21
30
50
70
%
T_PCLK−1.5 T_PCLK T_PCLK+1.5 ns
4T_PCLK
-
2T_PCLK
-
0
-
2.5
-
6
-
2.5
-
9
-
8
-
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
20
ns
13
ns
-
9.5
13
ns
-
9.5
17
ns
5.5
-
-
ns
3.5
-
-
ns
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