STM690A Datasheet, PDF (10/37 Pages) STMicroelectronics – 5V Supervisor with Battery Switchover

STM690A/692A/703/704/802/805/817/818/819
Back-up Battery Switchover
In the event of a power failure, it may be necessary
to preserve the contents of external SRAM
through V_OUT. With a backup battery installed with
voltage V_BAT, the devices automatically switch the
SRAM to the back-up supply when V_CC falls.
Note: If back-up battery is not used, connect both
V_BAT and V_OUT to V_CC.
This family of Supervisors does not always con-
nect V_BAT to V_OUT when V_BAT is greater than V_CC.
V_BAT connects to V_OUT (through a 100Ω switch)
when V_CC is below V_RST and V_BAT. This is done to
allow the back-up battery (e.g., a 3.6V lithium cell)
to have a higher voltage than V_CC.
Assuming V_BAT > 2.0V, switchover at V_SO ensures
that battery back-up mode is entered before V_OUT
gets too close to the 2.0V minimum required to re-
liably retain data in most external SRAMs. When
V_CC recovers, hysteresis is used to avoid oscilla-
tion around the V_SO point. V_OUT is connected to
V_CC through a 3Ω PMOS power switch.
Note: The back-up battery may be removed while
V_CC is valid, assuming V_BAT is adequately decou-
pled (0.1µF typ), without danger of triggering a re-
set.
Table 4. I/O Status in Battery Back-up
Pin
Status
V_OUT Connected to V_BAT through internal switch
V_CC Disconnected from V_OUT
PFI Disabled
PFO Logic low
E High impedance
E_CON Logic high
WDI Watchdog timer is disabled
WDO Logic low
MR Disabled
RST Logic low
RST Logic high
V_BAT Connected to V_OUT
Chip-Enable Gating (STM818 only)
Internal gating of the chip enable (E) signal pre-
vents erroneous data from corrupting the external
CMOS RAM in the event of an undervoltage con-
dition. The STM818 uses a series transmission
gate from E to E_CON (see Figure 12., page 11).
During normal operation (reset not asserted), the
E transmission gate is enabled and passes all E
transitions. When reset is asserted, this path be-
comes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short E propaga-
tion delay from E to E_CON enables the STM818 to
be used with most µPs. If E is low when reset as-
serts, E_CON remains low for typically 15µs to per-
mit the current WRITE cycle to complete. Connect
E to V_SS if unused.
Chip Enable Input (STM818 only)
The chip-enable transmission gate is disabled and
E is high impedance (disabled mode) while reset
is asserted. During a power-down sequence when
V_CC passes the reset threshold, the chip-enable
transmission gate disables and E immediately be-
comes high impedance if the voltage at E is high.
If E is low when reset asserts, the chip-enable
transmission gate will disable 15µs after reset as-
serts (see Figure 13., page 11). This permits the
current WRITE cycle to complete during power-
down.
Any time a reset is generated, the chip-enable
transmission gate remains disabled and E remains
high impedance (regardless of E activity) for the
reset time-out period. When the chip enable trans-
mission gate is enabled, the impedance of E ap-
pears as a 40Ω resistor in series with the load at
E_CON. The propagation delay through the chip-en-
able transmission gate depends on V_CC, the
source impedance of the drive connected to E,
and the loading on E_CON. The chip enable propa-
gation delay is production tested from the 50%
point on E to the 50% point on E_CON using a 50Ω
driver and a 50pF load capacitance (see Figure
40., page 28). For minimum propagation delay,
minimize the capacitive load at E_CON and use a
low-output impedance driver.
Chip Enable Output (STM818 only)
When the chip-enable transmission gate is en-
abled, the impedance of E_CON is equivalent to a
40Ω resistor in series with the source driving E. In
the disabled mode, the transmission gate is off
and an active pull-up connects E_CON to V_OUT (see
Figure 12., page 11). This pull-up turns off when
the transmission gate is enabled.
10/37