STD90NH02L Datasheet, PDF (10/12 Pages) STMicroelectronics – N-CHANNEL 24V - 0.0052 ohm - 60A DPAK/IPAK STripFET™ III POWER MOSFET

STD90NH02L
APPENDIX A
Buck Converter: Power Losses Estimation
SW1
SW2
The power losses associated with the FETs in a Synchronous Buck converter can be
estimated using the equations shown in the table below. The formulas give a good
approximation, for the sake of performance comparison, of how different pairs of devices
affect the converter efficiency. However a very important parameter, the working
temperature, is not considered. The real device behavior is really dependent on how the
heat generated inside the devices is ermoved to allow for a safer working junction
temperature.
The low side (SW2) device requires:
• Very low R_DS(on) to reduce conduction losses
• Small Q_gls to reduce the gate charge losses
• Small C_oss to reduce losses due to output capacitance
• Small Q_rr to reduce losses on SW₁ during its turn-on
• The C_gd/C_gs ratio lower than V_th/V_gg ratio especially with low drain to source
voltage to avoid the cross conduction phenomenon;
The high side (SW1) device requires:
• Small R_g and L_s to allow higher gate current peak and to limit the voltage
feedback on the gate
• Small Q_g to have a faster commutation and to reduce gate charge losses
• Low R_DS(on) to reduce the conduction losses.
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