S2-LP Datasheet, PDF (10/90 Pages) STMicroelectronics – Excellent receiver selectivity and blocking

Detailed functional description
Figure 1: Simplified S2-LP block diagram
S2-LP
The receiver architecture is low-IF conversion, the received RF signal is amplified by a two-
stage low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the
intermediate frequency (IF). LNA and IF amplifiers make up the RX front-end (RXFE) and
have programmable gain. At IF, the ADCs digitalize the I/Q signals. The demodulated data
go to an external MCU either through the 128-byte RX FIFO, readable via SPI, or directly
using a programmable GPIO pin.
The transmitter part of the S2-LP is based on direct synthesis of the RF frequency. The
power amplifier (PA) input is the LO generated by the RF synthesizer, while the output level
can be configured between -30 dBm and +14 dBm (+16 dBm in boost mode), at pin level
with 0.5 dB steps.
The data to be transmitted can be provided by an external MCU either through the 128-
byte TX FIFO writable via SPI, or directly using a programmable GPIO pin. The S2-LP
supports frequency hopping, TX/RX and antenna diversity switch control, extending the link
range and improving performance.
The S2-LP has a very efficient power management (PM) system. An integrated switched
mode power supply (SMPS) regulator allows operation from a battery voltage ranging from
+1.8 V to +3.6 V, and with power conversion efficiency of 90%.
A crystal must be connected between XIN and XOUT. It is digitally configurable to operate
with different crystals. As an alternative, an external clock signal can be used to feed XIN
for proper operation. The S2-LP also has an integrated low-power RC oscillator, generating
the 34.7 kHz signal used as a clock for the slowest timeouts.
A standard 4-pin SPI bus is used to communicate with the external MCU. Four configurable
general purpose I/Os are available.
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