M36W108T Datasheet, PDF (10/35 Pages) STMicroelectronics – 8 Mbit 1Mb x8, Boot Block Flash Memory and 1 Mbit 128Kb x8 SRAM Low Voltage Multi-Memory Product

M36W108T, M36W108B
Table 9. Flash Instructions ⁽¹⁾
Mne.
Instr. Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
Read/Reset
RD ^{(2,4) Memory}
Array
Addr. ^(3,7)
1+
Data
Addr. ^(3,7)
3+
Data
X
Read Memory Array until a new write cycle is initiated.
F0h
5555h
AAh
2AAAh
55h
5555h _{Read Memory Array until a new write cycle}
F0h ^{is initiated.}
AS ^{(4) Auto Select}
Addr. ^(3,7)
3+
Data
5555h
AAh
2AAAh
55h
5555h ^{Read Electronic Signature or Block}
Protection Status until a new write cycle is
90h initiated. See Note 5 and 6.
PG Program
Addr. ^{(3,7) 5555h}
4
Data
AAh
2AAAh
55h
5555h
A0h
Program
Address _{Read Data Polling or Toggle Bit}
Program ^{until Program completes.}
Data
BE Block Erase
Addr. ^{(3,7) 5555h}
6
Data
AAh
2AAAh
55h
5555h
80h
5555h
AAh
2AAAh
55h
Block Additional
Address _Block ⁽⁸⁾
30h
30h
CE Chip Erase
Addr. ^{(3,7) 5555h}
6
Data
AAh
2AAAh
55h
5555h
80h
5555h
AAh
2AAAh
55h
5555h
10h
Note 9
ES ⁽¹⁰⁾
Erase
Suspend
Addr. ^(3,7)
1
Data
X
Read until Toggle stops, then read all the data needed from any
B0h ^{Block(s) not being erased then Resume Erase.}
ER
Erase
Resume
Addr. ^(3,7)
1
Data
X
Read Data Polling or Toggle Bits until Erase completes or Erase
30h ^{is suspended another time.}
Note: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of t_PLYH is necessary after a Read/Reset command if the memory was in an Erase, Erase Suspend or Program mode before
starting any new operation (see Table 14 and Figure 7).
3. X = Don’t care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
mand cycles.
5. Signature Address bits A0, A1, at V_IL will output Manufacturer code (20h). Address bits A0 at V_IH and A1, at V_IL will output Device
code.
6. Block Protection Address: A0, at V_IL, A1 at V_IH and A13-A19 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15-A19 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be
verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, real Data Polling or Toggle bit
until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
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