STD20N06 Datasheet, PDF (1/10 Pages) STMicroelectronics – N - CHANNEL ENHANCEMENT MODE ”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR

STD20N06
N - CHANNEL ENHANCEMENT MODE
”ULTRA HIGH DENSITY” POWER MOS TRANSISTOR
TYPE
STD20N06
VDSS
60 V
R DS( on)
< 0.03 Ω
ID
20 A (*)
s TYPICAL R_DS(on) = 0.026 Ω
s AVALANCHE RUGGED TECHNOLOGY
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100^oC
s HIGH CURRENT CAPABILITY
s 175^oC OPERATING TEMPERATURE
s HIGH dV/dt RUGGEDNESS
s THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX ”-1”)
s SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX ”T4”)
DESCRIPTION
This series of POWER MOSFETS represents the
latest development in low voltage technology.
The ultra high cell density process (UHD) produ-
ced with fine geometries on advanced equipment
gives the device extremely low R_DS(on) as well as
good switching performance and high avalanche
energy capability.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s POWER MOTOR CONTROL
s DC-DC & DC-AC CONVERTERS
s SYNCRONOUS RECTIFICATION
ABSOLUTE MAXIMUM RATINGS
PRELIMINARY DATA
3
2
1
IPAK
TO-251
(Suffix ”-1”)
3
1
DPAK
TO-252
(Suffix ”T4”)
INTERNAL SCHEMATIC DIAGRAM
Symbol
P ar amete r
V_{D S} Drain-source Voltage (V_GS = 0)
VDG R Drain- gate Voltage (RGS = 20 kΩ)
V_GS Gate-source Voltage
I_D
Drain Current (continuous) at T _c = 25 ^oC
ID
Drain Current (continuous) at T c = 100 ^oC
I_{D M}(•)
P_tot
Drain Current (pulsed)
Total Dissipation at T_c = 25 ^oC
Derating Factor
T_stg Storage Temperature
T_j
Max. Operating Junction Temperature
(*) Current limited by the package
(•) Pulse width limited by safe operating area (*)
Value
60
60
± 20
20
14
80
60
0.4
-65 to 175
175
Unit
V
V
V
A
A
A
W
W /^o C
o_C
o_C
March 1995
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