STB85NF3LL Datasheet, PDF (1/9 Pages) STMicroelectronics – N-CHANNEL 30V - 0.006ohm - 85A D2PAK LOW GATE CHARGE STripFET™II POWER MOSFET

STB85NF3LL
N-CHANNEL 30V - 0.006Ω - 85A D²PAK
LOW GATE CHARGE STripFET™II POWER MOSFET
TYPE
V_DSS
R_DS(on)
I_D
STB85NF3LL
30 V < 0.008 Ω 85 A
s TYPICAL R_DS(on) = 0.0075Ω (@4.5V)
s OPTIMAL R_DS(on) x Qg TRADE-OFF @4.5V
s CONDUCTION LOSSES REDUCED
s SWITCHING LOSSES REDUCED
s ADD SUFFIX “T4” FOR ORDERING IN TAPE &
REEL
DESCRIPTION
This application specific Power MOSFET is the third
genaration of STMicroelectronics unique “ Single
Feature Size” strip-based process. The resulting
transistor shows the best trade-off between on-re-
sistance and gate charge. When used as high and
low side in buck regulators, it gives the best perfor-
mance in terms of both conduction and switching
losses. This is extremely important for mother-
boards where fast switching and high efficiency are
of paramount importance.
APPLICATIONS
s SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V_DS
Drain-source Voltage (V_GS = 0)
V_DGR
Drain-gate Voltage (R_GS = 20 kΩ)
V_GS
Gate- source Voltage
V_GSM
Gate-source Voltage Pulsed
(t_p≤50µs; duty cycle 25%; T_j ≤ 150°C)
I_D
Drain Current (continuos) at T_C = 25°C
I_D
Drain Current (continuos) at T_C = 100°C
I_DM (l) Drain Current (pulsed)
P_TOT
Total Dissipation at T_C = 25°C
Derating Factor
T_stg
Storage Temperature
T_j
Max. Operating Junction Temperature
(q) Pulse width limited by safe operating area
November 2001
3
1
D²PAK
INTERNAL SCHEMATIC DIAGRAM
Value
30
30
± 16
± 20
85
60
340
110
0.73
–65 to 175
175
Unit
V
V
V
V
A
A
A
W
W/°C
°C
°C
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