M36LLR8760T1 Datasheet, PDF (1/19 Pages) STMicroelectronics – 256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package

M36LLR8760T1, M36LLR8760D1
M36LLR8760M1, M36LLR8760B1
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package
TARGET SPECIFICATION
FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
– 1 die of 256 Mbit (16Mb x16, Multiple
Bank, Multi-level, Burst) Flash Memory
– 1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-Level, Burst) Flash Memory
– 1 die of 64 Mbit (4Mb x16) Pseudo SRAM
■ SUPPLY VOLTAGE
– V_DDF1 = V_DDF2 = V_CCP = V_DDQF = 1.7 to
1.95V
– V_PPF = 9V for fast program (12V tolerant)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Configuration (Top + Top)
M36LLR8760T1: 880Dh + 88C4h
– Mixed Configuration (Bottom + Top)
M36LLR8760D1: 880Eh + 88C4h
– Mixed Configuration (Top + Bottom)
M36LLR8760M1: 880Dh + 88C5h
– Bottom Configuration (Bottom + Bottom)
M36LLR8760B1: 880Eh + 88C5h
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORIES
■ SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous Page Read mode
– Random Access: 85ns
■ SYNCHRONOUS BURST READ SUSPEND
■ PROGRAMMING TIME
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
■ MEMORY ORGANIZATION
– Multiple Bank Memory Array:
16 Mbit Banks for the 256 Mbit Memory
8 Mbit Banks for the 128 Mbit Memory
– Parameter Blocks (at Top or Bottom)
Figure 1. Package
FBGA
LFBGA88 (ZAQ)
8 x 10mm
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP_F for Block Lock-Down
– Absolute Write Protection with V_PPF = V_SS
PSRAM
■ ACCESS TIME: 70ns
■ ASYNCHRONOUS PAGE READ
– Page Size: 16 words
– Subsequent read within page: 20ns
■ LOW POWER FEATURES
– Temperature Compensated Refresh
(TCR)
– Partial Array Refresh (PAR)
– Deep Power-Down (DPD) Mode
■ SYNCHRONOUS BURST READ/WRITE
July 2005
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.
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