HCF4021B Datasheet, PDF (1/11 Pages) STMicroelectronics – ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER

HCF4021B
ASYNCHRONOUS PARALLEL IN OR SYNCHRONOUS
SERIAL IN/SERIAL OUT 8 - STAGE STATIC SHIFT REGISTER
s MEDIUM SPEED OPERATION : 12 MHz
(Typ.) CLOCK RATE AT V_DD - V_SS = 10V
s FULLY STATIC OPERATION
s 8 MASTER-SLAVE FLIP-FLOPS PLUS
OUTPUT BUFFERING AND CONTROL
GATING
s QUIESCENT CURRENT SPECIFIED UP TO
20V
s 5V, 10V AND 15V PARAMETRIC RATINGS
s INPUT LEAKAGE CURRENT
I_I = 100nA (MAX) AT V_DD = 18V T_A = 25°C
s 100% TESTED FOR QUIESCENT CURRENT
s MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4021B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is an 8-stage parallel or serial input/
serial output register having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single
SERIAL data input, and individual parallel "JAM"
inputs to each register stage. Each register stage
is a D-type, master-slave flip-flop in addition to an
output from stage 8, "Q" outputs are also available
from stages 6 and 7. Serial entry is synchronous
with the clock but parallel entry is asynchronous.
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF4021BEY
HCF4021BM1
T&R
HCF4021M013TR
In this device, entry is controlled by the
PARALLEL/SERIAL CONTROL input. When the
PARALLEL/SERIAL CONTROL input is low, data
is serially shifted into the 8-stage register
synchronously with the positive transition of he
clock line. When the PARALLEL/SERIAL
CONTROL input is high, data is jammed into the
8-stage register via the parallel input lines and
synchronous with the positive transition of the
clock line, the CLOCK input of the internal stage is
"forced" when asynchronous parallel entry is
made. Register expansion using multiple package
is permitted.
PIN CONNECTION
September 2001
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