HCC40100B Datasheet, PDF(1/13 Page) STMicroelectronics – 32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER

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HCC40100B Datasheet, PDF (1/13 Pages) STMicroelectronics – 32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER

HCC/HCF40100B

32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER

. FULLY STATIC OPERATION

. SHIFT LEFT/SHIFT RIGHT CAPABILITY

. MULTIPLE PACKAGE CASCADING

. RECIRCULATE CAPABILITY

. LIFO OR FIFO CAPABILITY

. STANDARDIZED SYMMETRICAL OUTPUT

CHARACTERISTICS

. QUIESCENT CURRENT SPECIFIED AT 20V

FOR HCC DEVICE

. 5V, 10V, AND 15V PARAMETRIC RATINGS

. INPUT CURRENT OF 100nA AT 18V AND 25Â°C

FOR HCC DEVICE

. 100% TESTED FOR QUIESCENT CURRENT

. MEETS ALL REQUIREMENTS OF JEDECTEN-

TATIVE STANDARD No. 13A, âSTANDARD

SPECIFICATIONS FOR DESCRIPTION OF âBâ

SERIES CMOS DEVICESâ

data in the 32nd stage is shifted into the first stage

when the LEFT/RIGHT CONTROL is low and from

the 1st stage to the 32nd stage when the

LEFT/RIGHT CONTROL is high.

(Plastic Package) (Ceramic Frit Seal Package)

DESCRIPTION

The HCC40100B (extended temperature range)

and HCF40100B (intermediate temperature range)

are monolithic integrated circuits, available in 16-

lead dual in-line plastic or ceramic package and

plastic micro package. The HCC/HCF40100B is a

32-stage shift register containing 32 D-type master-

slave flip-flops. The data present at the SHIFT-

RIGHT INPUT is transferred into the first register

stage synchronously with the positive CLOCK edge,

provided the LEFT/RIGHT CONTROL is at a low

level, the RECIRCULATE CONTROL is at a high

level, and the CLOCK INHIBIT is low. If the

LEFT/RIGHT CONTROL is at a high level and the

RECIRCULATE CONTROL is also high, data at the

SHIFT-LEFT INPUT is transferred into the 32nd reg-

ister stage synchronously with the positive CLOCK

transition, provided the CLOCK INHIBIT is low. The

state of the LEFT/RIGHT CONTROL, RECIRCU-

LATE CONTROL, and CLOCK INHIBIT should not

be changed when the CLOCK is high. Data is shifted

one stage left or one stage right depending on the

state of the LEFT/RIGHT CONTROL, synchron-

ously with the positive CLOCK edge. Data clocked

into the first or 32nd register states is available at the

SHIFT-LEFT or SHIFT-RIGHT OUTPUT respec-

tively, on the next negative CLOCK transition (see

Data Transfer Table). No shifting occurs on the posi-

tive CLOCK edge if the CLOCK INHIBIT line is at a

high level. With the RECIRCULATE CONTROL low,

(Micro Package)

(Plastic Chip Carrier)

ORDER CODES :

HCC40100BF HCF40100BM1

HCF40100BEY HCF40100BC1

PIN CONNECTIONS

June 1989

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