SST32HF32A2 Datasheet, PDF (6/35 Pages) Silicon Storage Technology, Inc – Multi-Purpose Flash Plus + PSRAM ComboMemory

Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF32A2
Preliminary Specifications
Product Identification Mode Exit/Reset
In order to return to the standard read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
internal Program or Erase operation. This command may
also be used to reset the device to Read mode after any
inadvertent transient condition that apparently causes the
device to behave abnormally, e.g. not read correctly. See
Table 5 for software command codes, Figure 15 for timing
waveform and Figure 23 for a flowchart.
Security ID
The SST32HF32A2 devices offer a 256-bit Security ID
space. The Secure ID space is divided into two 128-bit seg-
ments - one factory programmed segment and one user
programmed segment. The first segment is programmed
and locked at SST with a random 128-bit number. The user
segment is left un-programmed for the customer to pro-
gram as desired.
To program the user segment of the Security ID, the user
must use the Security ID Word-Program command. To
detect end-of-write for the SEC ID, read the toggle bits. Do
not use Data# Polling. Once this is complete, the Sec ID
should be locked using the User Sec ID Program Lock-Out.
This disables any future corruption of this space. Note that
regardless of whether or not the Sec ID is locked, neither
Sec ID segment can be erased.
The Secure ID space can be queried by executing a three-
byte command sequence with Enter Sec ID command
(88H) at address 5555H in the last byte sequence. To exit
this mode, the Exit Sec ID command should be executed.
Refer to Table 5 for more details.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between V_DD and
V_SS, e.g., less than 1 cm away from the V_DD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from V_DD to V_SS should be placed within 1 cm of
the V_DD pin.
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
A_MS-A₀
UBS#
LBS#
BES1#
BES2
BEF#
OE¹#
WE¹#
WP#
RESET#
Control Logic
PSRAM
I/O Buffers
DQ15 - DQ8
DQ7 - DQ0
Address Buffers
& Latches
SuperFlash
Memory
Notes: 1. For LS package only: WE# = WEF# and/or WES#
OE# = OEF# and/or OES#
1261 B1.1
©2005 Silicon Storage Technology, Inc.
6
S71261-01-000
5/05