SST32HF32A2 Datasheet, PDF (16/35 Pages) Silicon Storage Technology, Inc – Multi-Purpose Flash Plus + PSRAM ComboMemory

Preliminary Specifications
Multi-Purpose Flash Plus + PSRAM ComboMemory
SST32HF32A2
ADDRESSES AMSS³-0
WE#
BES1#
TASTS
T_WCS
T_WPS
TAWS
TBWS
TWRS
BES2
TBWS
UBS#, LBS#
TODWS
TBYWS
T_DSS
T_OEWS
TDHS
DQ15-8, DQ7-0
NOTE 2
VALID DATA IN
NOTE 2
1261 F04.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. If BES1# goes Low or BES2 goes high coincident with or after WE# goes Low, the output will remain at high impedance.
If BES1# goes High or BES2 goes low coincident with or before WE# goes High, the output will remain at high impedance.
Because D_IN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. A_MSS = Most Significant PSRAM Address
A_MSS = A₁₉ for SST32HF32A2
FIGURE 4: PSRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)¹
©2005 Silicon Storage Technology, Inc.
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S71261-01-000
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