SST89E52RC Datasheet, PDF (53/57 Pages) Silicon Storage Technology, Inc – FlashFlex MCU

FlashFlex MCU
SST89E52RC / SST89E54RC
TO DUT
1259 F38.0
FIGURE 12-8: A Test Load Example
VDD
RST
VDD
VDD
IDD
VDD
P0
EA#
CLOCK ^(NC)
SIGNAL
XTAL2
XTAL1
VSS
1259 F39.0
All other pins disconnected
FIGURE 12-9: I_DD Test Condition,
Active Mode
RST
VDD
VDD
IDD
VDD
P0
EA#
CLOCK ^(NC)
SIGNAL
XTAL2
XTAL1
VSS
All other pins disconnected
1259 F40.0
FIGURE 12-10: I_DD Test Condition,
Idle Mode
TO TESTER
CL
Data Sheet
V_DD = 2V
VDD
VDD
IDD
VDD
P0
RST
EA#
(NC)
XTAL2
XTAL1
VSS
All other pins disconnected
1259 F41.0
FIGURE 12-11: I_DD Test Condition,
Power-down Mode
TABLE 12-10: Flash Memory Programming/
Verification Parameters¹
Parameter²
Max Units
Chip-Erase Time
350 ms
Block-Erase Time
300 ms
Sector-Erase Time
Byte-Program Time³
30
ms
100 µs
Re-map or Security bit Program Time
100 µs
T12-10.0 1259
1. For IAP operations, the program execution overhead
must be added to the above timing parameters.
2. Program and Erase times will scale inversely proportional
to programming clock frequency.
3. Each byte must be erased before programming.
©2007 Silicon Storage Technology, Inc.
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