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SST89E52RC Datasheet, PDF (1/57 Pages) Silicon Storage Technology, Inc – FlashFlex MCU | |||
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FlashFlex MCU
SST89E52RC / SST89E54RC
FEATURES:
⢠8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
â Fully Software Compatible
â Development Toolset Compatible
â Pin-for-Pin Package Compatible
⢠SST89E5xRC Operation
â 0 to 33MHz at 5V
⢠Total 512 Byte Internal RAM
(256 Byte by default +
256 Byte enabled by software)
⢠Single Block SuperFlash EEPROM
â SST89E54RC: 16 KByte primary partition +
1 KByte secondary partition
â SST89E52RC: 8 KByte primary partition +
1 KByte secondary partition
â Primary Partition is divided into Four Pages
â Secondary Partition has One Page
â Individual Page Security Lock
â In-System Programming (ISP)
â In-Application Programming (IAP)
â Small-Sector Architecture: 128-Byte Sector Size
⢠Support External Address Range up to 64
KByte of Program and Data Memory
⢠Three High-Current Port 1 pins (16 mA each)
⢠Three 16-bit Timers/Counters
Data Sheet
⢠Full-Duplex, Enhanced UART
â Framing error detection
â Automatic address recognition
⢠Eight Interrupt Sources at 4 Priority Levels
⢠Programmable Watchdog Timer (WDT)
⢠Four 8-bit I/O Ports (32 I/O Pins)
⢠Second DPTR register
⢠Low EMI Mode (Inhibit ALE)
⢠Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
⢠TTL- and CMOS-Compatible Logic Levels
⢠Low Power Modes
â Power-down Mode with External Interrupt Wake-up
â Idle Mode
⢠Selectable Operation Clock
â Divide down to 1/4, 1/16, 1/256, or 1/1024th
⢠Temperature Ranges:
â Commercial (0°C to +70°C)
⢠Packages Available
â 40-pin PDIP
â 44-lead PLCC
⢠All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST89E52RC / SST89E54RC are members of the
FlashFlex family of 8-bit microcontroller products designed
and manufactured with SSTâs patented and proprietary
SuperFlash CMOS semiconductor process technology.
The split-gate cell design and thick-oxide tunneling injector
offer significant cost and reliability benefits for our custom-
ers.The devices use the 8051 instruction set and are pin-
for-pin compatible with standard 8051 microcontroller
devices.
The device comes with 17/9 KByte of on-chip flash
EEPROM program memory which is divided into 2 inde-
pendent program memory partitions. The primary partition
occupies 16/8 KByte of internal program memory space
and the secondary partition occupies 1 KByte of internal
program memory space.
The flash memory can be programmed via a standard
87C5x OTP EPROM programmer fitted with a special
adapter and firmware for SSTâs devices. During power-on
reset, the devices can be configured as either a slave to an
external host for source code storage or a master to an
external host for an in-system programming (ISP) opera-
tion. The devices are designed to be programmed in-sys-
tem on the printed circuit board for maximum flexibility. An
example of the bootstrap loader (BSL) in memory, demon-
strating initial user program code loading or subsequent
user code updating via an ISP operation, is provided on the
SST website. The sample BSL is for the userâs reference
only; SST does not guarantee its functionality.
In addition to 17/9 KByte of SuperFlash EEPROM program
memory on-chip and 512 x8 bits of on-chip RAM, the
device can address up to 64 KByte of external program
memory and up to 64 KByte of external RAM.
The highly-reliable, patented SST SuperFlash technology
and memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant cost
and reliability benefits for our customers.
©2007 Silicon Storage Technology, Inc.
S71259-04-000
1/07
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
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