SST34HF3244C Datasheet, PDF (4/40 Pages) Silicon Storage Technology, Inc – 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory

32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory
SST34HF3244C
Data Sheet
Flash Write Operation Status Detection
The SST34HF3244C provide one hardware and two soft-
ware means to detect the completion of a Write (Program
or Erase) cycle, in order to optimize the system Write
cycle time. The hardware detection uses the Ready/
Busy# (RY/BY#) pin. The software detection includes two
status bits: Data# Polling (DQ₇) and Toggle Bit (DQ₆).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE#, which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), Data# Polling (DQ₇) or Toggle Bit (DQ₆) read may be
simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result,
i.e., valid data may appear to conflict with either DQ₇ or
DQ₆. In order to prevent spurious rejection, if an erroneous
result occurs, the software routine should include a loop to
read the accessed location an additional two (2) times. If
both reads are valid, then the device has completed the
Write cycle, otherwise the rejection is valid.
Ready/Busy# (RY/BY#)
The SST34HF3244C include a Ready/Busy# (RY/BY#)
output signal. RY/BY# is an open drain output pin that indi-
cates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to V_DD via an external
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (CIOF)
The device includes a CIOF pin to control whether the
device data I/O pins operate x8 or x16. If the CIOF pin is at
logic “1” (V_IH) the device is in x16 data configuration: all
data I/0 pins DQ₀-DQ₁₅ are active and controlled by BEF#
and OE#.
If the CIOF pin is at logic “0”, the device is in x8 data config-
uration: only data I/O pins DQ₀-DQ₇ are active and con-
trolled by BEF# and OE#. The remaining data pins DQ₈-
DQ₁₄ are at Hi-Z, while pin DQ₁₅ is used as the address
input A_-1 for the Least Significant Bit of the address bus.
Flash Data# Polling (DQ₇)
When the devices are in an internal Program operation, any
attempt to read DQ₇ will produce the complement of the
true data. Once the Program operation is completed, DQ₇
will produce true data. During internal Erase operation, any
attempt to read DQ₇ will produce a ‘0’. Once the internal
Erase operation is completed, DQ₇ will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
BEF#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or BEF#) pulse. See Figure 10 for Data# Poll-
ing (DQ₇) timing diagram and Figure 23 for a flowchart.
©2006 Silicon Storage Technology, Inc.
4
S71282-02-000
8/06