SST49LF030A Datasheet, PDF (25/49 Pages) Silicon Storage Technology, Inc – 3 Mbit LPC Flash

3 Mbit LPC Flash
SST49LF030A
EOL Product Data Sheet
CE#
LCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
CE#
LCLK
Memory
1st Start
Write
Cycle
Address¹
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b 0101b 1010b 1010b 1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "YYYY 5555H" in 8 Clocks
Load Data "AAH" in 2 Clocks 2 Clocks
1 Clock
Write the 1st command to the device in LPC mode.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Start next
Command
1 Clock
LFRAME#
LAD[3:0]
CE#
LCLK
Memory
2nd Start
Write
Cycle
Address¹
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b 0101b 1010b 1010b 1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "YYYY 2AAAH" in 8 Clocks
Load Data "55H" in 2 Clocks 2 Clocks
Write the 2nd command to the device in LPC mode.
1 Clock
Start next
Command
1 Clock
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
CE#
LCLK
Memory
3rd Start
Write
Cycle
Address¹
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b 0101b 1010b 1010b 1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "YYYY 5555H" in 8 Clocks
Load Data "80H" in 2 Clocks 2 Clocks
Write the 3rd command to the device in LPC mode.
1 Clock
Start next
Command
1 Clock
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
LFRAME#
LAD[3:0]
CE#
LCLK
Memory
4th Start
Write
Cycle
Address¹
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b 0101b 1010b 1010b 1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "YYYY 5555H" in 8 Clocks
Load Data "AAH" in 2 Clocks 2 Clocks
Write the 4th command to the device in LPC mode.
1 Clock
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Start next
Command
1 Clock
LFRAME#
LAD[3:0]
CE#
LCLK
LFRAME#
LAD[3:0]
Memory
5th Start
Write
Cycle
Address¹
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b 0101b 1010b 1010b 1111b Tri-State 0000b
TAR
1 Clock 1 Clock
Load Address "YYYY 2AAAH" in 8 Clocks
Load Data "55H" in 2 Clocks 2 Clocks
Write the 5th command to the device in LPC mode.
1 Clock
Start next
Command
1 Clock
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Memory
6th Start
Write
Cycle
Address¹
Data
TAR
Sync
0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] BAX XXXXb XXXXb XXXXb 0000b 0101b 1111b Tri-State 0000b
1 Clock 1 Clock
Load Block Address in 8 Clocks
Load Data "50H" in 2 Clocks 2 Clocks
1 Clock
Write the 6th command (target block to be erased) to the device in LPC mode.
BAX = Block Address
Note: 1. Address must be within memory address range specified in Table 4.
Internal
erase start
Internal
erase start
TAR
1234 F10.1
FIGURE 11: Block-Erase Command Sequence (LPC Mode)
©2005 Silicon Storage Technology, Inc.
25
S71234-03-EOL
5/06