SST39VF6401B Datasheet, PDF (17/30 Pages) Silicon Storage Technology, Inc – 64 Mbit (x16) Multi-Purpose Flash Plus

64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
ADDRESS AMS-0
SIX-BYTE CODE FOR BLOCK-ERASE
555
2AA
555
555
2AA
BAX
Data Sheet
TBE
CE#
OE#
WE#
TWP
DQ15-0
XXAA XX55
XX80
XXAA
XX55
XX30
SW0
SW1
SW2
SW3
SW4
SW5
1288 F09.0
Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
BA_X = Block Address
A_MS = Most significant address
A_MS = A₂₁ for SST39VF640xB
WP# must be held in proper logic state (V_IL or V_IH) 1 µs prior to and 1 µs after the command sequence.
X can be V_IL or V_IH, but no other value.
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE FOR SECTOR-ERASE
TSE
ADDRESS AMS-0
555
2AA
555
555
2AA
SAX
CE#
OE#
WE#
TWP
DQ15-0
XXAA XX55
XX80
XXAA
XX55
XX50
SW0
SW1
SW2
SW3
SW4
SW5
Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 15)
SA_X = Sector Address
A_MS = Most significant address
A_MS = A₂₁ for SST39VF640xB
WP# must be held in proper logic state (V_IL or V_IH) 1 µs prior to and 1 µs after the command sequence.
X can be V_IL or V_IH, but no other value.
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
1288 F10.0
©2006 Silicon Storage Technology, Inc.
17
S71288-02-000
7/06