SST25LF020A_10 Datasheet, PDF (10/25 Pages) Silicon Storage Technology, Inc – 2 Mbit SPI Serial Flash

Data Sheet
High-Speed-Read (33 MHz)
The High-Speed-Read instruction supporting up to 33 MHz
is initiated by executing an 8-bit command, 0BH, followed
by address bits [A₂₃-A₀] and a dummy byte. CE# must
remain active low for the duration of the High-Speed-Read
cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy byte (8 clocks input dummy cycle), the
High-Speed-Read instruction outputs the data starting from
the specified address location. The data output stream is
continuous through all addresses until terminated by a low
2 Mbit SPI Serial Flash
SST25LF020A
to high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
2 Mbit density, once the data from address location
03FFFFH has been read, the next output will be from
address location 000000H.
CE#
MODE 3 0 1 2 3 4 5 6 7 8 _{15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80}
SCK _{MODE 0}
SI
0B
ADD. ADD. ADD.
X
MSB
MSB
SO
HIGH IMPEDANCE
N
D_OUT
N+1
D_OUT
N+2
D_OUT
N+3
D_OUT
N+4
D_OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (VIL or VIH)
MSB
1242 F05.0
FIGURE 6: High-Speed-Read Sequence
©2010 Silicon Storage Technology, Inc.
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