CY28416 Datasheet, PDF (9/14 Pages) Cypress Semiconductor – Next Generation FTG for Intel-R Architecture

CY28416
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tstable
<1.8 ms
Tdrive_PW RDN#
<300PS, >200mV
Figure 4. Power-down Deassertion Timing Waveform
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
VDD Clock Gen
Clock State State 0
0.2-0.3mS
Delay
State 1
W ait for
VTT_PW RGD#
Sample Sels
State 2
Device is not affected,
VTT_PW RGD# is ignored
State 3
Off
Clock Outputs
Off
Clock VCO
On
On
Figure 5. VTT_PWRGD# Timing Diagram
VDD_A = 2.0V
S0
Power Off
S1
VTT_PW RGD# = Low
Delay >0.25 m s
S2
Sam ple
Inputs straps
VDD_A = off
S3
N orm al
O p e ra tio n
VTT_PW RGD# = toggle
W ait for <1.8m s
Enable Outputs
Figure 6. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 22, 2006
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