CY28408 Datasheet, PDF (9/18 Pages) Cypress Semiconductor – Clock Synthesizer with Differential CPU Outputs

CY28408
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 3. CPU_STP# Assertion Waveform
CPU_STP#
CPUT
CPUC
CPUT
CPUC
Figure 4. CPU_STP# Deassertion Waveform
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all
CPUT/C outputs that were stopped to resume normal
operation in a synchronous manner. Synchronous manner
meaning that no short or stretched clock pulses will be
produces when the clock resumes. The maximum latency
from the deassertion to active outputs is no more than 2 CPUC
clock cycles.
Three-state Control of CPU Clocks Clarification
During CPU_STP# and PD# modes, CPU clock outputs may
be set to driven or undriven (three-state) by setting the corre-
sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.
Table 9. Cypress Clock Power Management Truth Table
B0b6
0
0
0
0
0
0
0
0
1
1
1
1
B1b6
0
0
0
0
1
1
1
1
0
0
0
0
PD# CPU_STP# Stoppable CPUT Stoppable CPUC Non-Stop CPUT Non-Stop CPUC
1
1
Running
Running
Running
Running
1
0
Iref x6
Iref x6
Running
Running
0
1
Iref x2
Low
Iref x2
Low
0
0
Iref x2
Low
Iref x2
Low
1
1
Running
Running
Running
Running
1
0
Hi Z
Hi Z
Running
Running
0
1
Hi Z
Hi Z
Hi Z
Hi Z
0
0
Hi Z
Hi Z
Hi Z
Hi Z
1
1
Running
Running
Running
Running
1
0
Iref x6
Iref x6
Running
Running
0
1
Hi Z
Hi Z
Hi Z
Hi Z
0
0
Hi Z
Hi Z
Hi Z
Hi Z
Rev 1.0, November 20, 2006
Page 9 of 18