CY28408 Datasheet, PDF (15/18 Pages) Cypress Semiconductor – Clock Synthesizer with Differential CPU Outputs

CY28408
AC Electrical Specifications (continued)
Parameter
Description
48M_USB
T_DC
Duty Cycle
T_PERIOD
Period
T_R / T_F
Rise and Fall Times
T_CCJ
Cycle to Cycle Jitter
REF
T_DC
REF Duty Cycle
T_PERIOD
REF Period
T_R / T_F
REF Rise and Fall Times
T_CCJ
REF Cycle to Cycle Jitter
ENABLE/DISABLE and SETUP
T_PZL/T_PZH Output Enable Delay (all outputs)
T_PLZ/T_PHZ Output Disable Delay (all outputs)
T_STABLE Clock Stabilization from Power-up
T_SS
Stopclock Setup Time
T_SH
Stopclock Hold Time
Condition
Measured at 1.5V
Measured at 1.5V
Measured at 0.4 to 2.4V
Measured at 1.5V. See Table 11
Measured at 1.5V
Measured at 1.5V
Measured at 0.4 to 2.4V
Measured at 1.5V. See Table 11
Table 11.Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
PCI Clocks
3V66
48M_USB Clock
48M_DOT
REF Clock
30
pF
30
pF
20
pF
10
pF
50
pF
Min.
45
20.8299
1.0
–
45
69.84
0.5
–
1.0
1.0
–
10.0
0
Max.
55
20.8333
2.0
350
55
71.0
2.0
1000
10.0
10.0
3.0
–
–
Unit
%
ns
ns
ps
%
ns
V/ns
ps
ns
ns
ms
ns
ns
Rev 1.0, November 20, 2006
Page 15 of 18