CY28347 Datasheet, PDF (8/21 Pages) Cypress Semiconductor – Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems

CY28347
Byte 8: Silicon Signature Register (all bits are Read-only)
Bit @Pup
Name
7
0
Revision_ID3
6
0
Revision_ID2
5
0
Revision_ID1
4
0
Revision_ID0
3
1
Vender_ID3
2
0
Vender_ID2
1
0
Vender_ID1
Revision ID bit [3]
Revision ID bit [2]
Revision ID bit [1]
Revision ID bit [0]
Cypress’s Vendor ID bit [3]
Cypress’s VendorID bit [2]
Cypress’s Vendor ID bit [1]
0
0
Vender_ID0
Cypress’s Vendor ID bit [0]
Description
Byte9: Dial-A-Frequency Control Register R
Bit @Pup
Name
7
0
6
0
R5, MSB
5
0
R4
4
0
R3
3
0
R2
Description
Reserved
These bits are for programming the PLL’s internal R register. This access allows
the user to modify the CPU frequency at very high resolution (accuracy). All other
synchronous clocks (clocks that are generated from the same PLL, such as PCI)
remain at their existing ratios relative to the CPU clock.
2
0
R1
1
0
R0
0
0
DAF_ENB
R and N register mux selection. 0=R and N values come from the ROM. 1=data is
load from DAF (I2C) registers.
Dial-a-Frequency Feature
Spread Spectrum Clock Generation (SSCG)
SMBus Dial-a-frequency feature is available in this device via
Byte7 and Byte9.
P is a PLL constant that depends on the frequency selection
prior to accessing the Dial-a-Frequency feature.
Table 9.
FS(4:0)
XXXXX
P
96016000
Spread Spectrum is enabled/disabled via SMBus register Byte
1, Bit 6.
Table 10. Spread Spectrum Table
Mode
0
0
0
0
1
1
1
1
SST1
0
0
1
1
0
0
1
1
SST0
0
1
0
1
0
1
0
1
% Spread
–1.5%
–1.0%
–0.7%
–0.5%
±0.75%
±0.5%
±0.35%
±0.25%
Rev 1.0, November 20, 2006
Page 8 of 21