CY28347 Datasheet, PDF (2/21 Pages) Cypress Semiconductor – Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems

CY28347
Pin Description ^[2]
Pin
Name
PWR I/O
Description
3
XIN
I Oscillator Buffer Input. Connect to a crystal or to an external clock.
4
XOUT
VDD
O Oscillator Buffer Output. Connect to a crystal. Do not connect when an external
clock is applied at XIN.
1
FS0/REF0
VDD I/O Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When the
PU power supply voltage crosses the input threshold voltage, FS0 state is latched and
this pin becomes REF0, buffered copy of signal applied at XIN. (1–2 x strength,
selectable by SMBus. Default value is 1 x strength.)
56
VTTPWRGD# VDDR I If SELP4_K7# = 1, with a P4 processor setup as CPU(T:C). At power-up,
VTT_PWRGD# is an input. When this input is sampled LOW, the FS (3:0) and
MULTSEL are latched and all output clocks are enabled. After the first transition to
a LOW on VTT_PWRGD#, this pin is ignored and will not effect the behavior of the
device thereafter. When the VTT_PWRGD# feature is not used, please connect this
signal to ground through a 10K:resistor.
REF1
VDDR
O If SELP4_K7# = 0, with an Athlon (K7) processor as CPUOD_(T:C).
VTT_PWRGD# function is disabled, and the feature is ignored. This pin becomes
REF1 and is a buffered copy of the signal applied at XIN.
44,42,38, DDRT(0:5)
36,32,30
VDDD O These pins are configured for DDR clock outputs. They are “True” copies of
signal applied at Pin45, BUF_IN.
43,41,37 DDRC(0:5)
35,31,29
VDDD O These pins are configured for DDR clock outputs. They are “Complementary”
copies of signal applied at Pin45, BUF_IN.
7
SELP4_K7#/ VDDAGP I/O Power-on Bidirectional Input/Output. At power-up, SELP4_K7# is the input.
AGP1
PU When the power supply voltage crosses the input threshold voltage, SELP4_K7#
state is latched and this pin becomes AGP1 clock output. SELP4_K7# = 1 selects
P4 mode. SELP4_K7# = 0 selects K7 mode.
12
MULTSEL/PCI2 VDDPCI I/O Power-on Bidirectional Input/Output. At power-up, MULTSEL is the input. When
PU the power supply voltage crosses the input threshold voltage, MULTSEL state is
latched and this pin becomes PCI2 clock output. MULTSEL = 0, Ioh is 4 x
IREFMULTSEL = 1, Ioh is 6 x IREF
53
CPUT/CPUOD_T VDDC O 3.3V True CPU Clock Outputs. This pin is programmable through strapping pin7,
SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUT Clock Output.
If SELP4_K7# = 0, this pin is configured as the CPUOD_T Open Drain Clock Output.
See Table 1.
52
CPUC/CPUOD_C VDDC O 3.3V Complementary CPU Clock Outputs. This pin is programmable through
strapping pin7, SELP4_K7#. If SELP4_K7# = 1, this pin is configured as the CPUC
Clock Output. If SELP4_K7# = 0, this pin is configured as the CPUOD_C Open
Drain Clock Output. See Table 1.
14,15,17 PCI (3:5)
VDDPCI O PCI Clock Outputs. Are synchronous to CPU clocks. See Table 1.
48,49 CPUCS_T/C VDDI O 2.5V CPU Clock Outputs for Chipset. See Table 1.
18
CPU_STP# VDDPCI I If pin 6 is pulled down at power on reset, then this pin becomes CPU_STP#. When
PU CPU_STP# is asserted LOW, then both of the CPU signals stop at the next HIGH
to LOW transition or stays LOW if it already is LOW. This does not stop the CPUCS
signals.
10
FS1/PCI_F VDDPCI I/O Power-on Bidirectional Input/Output. At power-up, FS1 is the input. When the
PD power supply voltage crosses the input threshold voltage, FS1 state is latched and
this pin becomes PCI_F clock output.
20
FS3/48M
VDD48M I/O Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When the
PD power supply voltage crosses the input threshold voltage, FS3 state is latched and
this pin becomes 48M, a USB clock output.
11
PCI1
VDDPCI O PCI Clock Output.
21
FS2/24_48M VDD48M I/O Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When the
PD power supply voltage crosses the input threshold voltage, FS2 state is latched and
this pin becomes 24_48M, a SIO programmable clock output.
Note:
2. PU = internal pull-up. PD = internal pull-down. Typically = 250 k: (range 200 k: to 500 k:).
Rev 1.0, November 20, 2006
Page 2 of 21