CY28346-2 Datasheet, PDF (8/19 Pages) Cypress Semiconductor – Clock Synthesizer with Differential CPU Outputs

CY28346-2
PWRDWN#
CPUT 133MHz
CPUC 133MHz
PCI 33MHz
AGP 66MHz
USB 48MHz
R EF 14.318M H z
DDRT 133MHz
DDRC 133MHz
SDRAM 133MHz
Figure 2. Power-down Assertion Timing Waveforms—Unbuffered Mode
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 3.0 ms.
66Buff1 / GMCH
66Buff
PCIF / APIC
33MHz
PCI 33MHz
PWRDWN#
CPU 133MHz
CPU# 133MHz
3V66
66In
USB 48MHz
REF 14.318MHz
<1.8mS
30uS min
400uS max
Figure 3. Power-down Deassertion Timing Waveforms
Table 5. PD# Functionality
PD#
DRCG
1
66M
0
Low
66CLK (0:2)
66Input
Low
PCIF/PCI
66Input/2
Low
PCI
66Input/2
Low
USB/DOT
48M
Low
Rev 1.0, November 20, 2006
Page 8 of 19