CY28346-2 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – Clock Synthesizer with Differential CPU Outputs

CY28346-2
Clock Synthesizer with Differential CPU Outputs
Features
• Compliant with Intel^® CK 408 Mobile Clock Synthesizer
specifications
• 3.3V power supply
• 3 differential CPU clocks
• 10 copies of PCI clocks
• 5/6 copies of 3V66 clocks
• SMBus support with Read Back capabilities
Table 1. Frequency Table^[1]
S2 S1 S0
CPU
(0:2)
3V66
100
66M
66M
1 0 1 100M
66M
1 1 0 200M
66M
1 1 1 133M
66M
000
66M
66M
0 0 1 100M
66M
0 1 0 200M
66M
0 1 1 133M
66M
M0 0
Hi-Z
Hi-Z
M 0 1 TCLK/2 TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66IN
66IN
66M
66M
66M
66M
Hi-Z
TCLK/4
• Spread Spectrum electromagnetic interference (EMI)
reduction
• Dial-a-Frequency^£ features
• Dial-a-dB™ features
• Extended operating temperature range, 0qC to 85qC
• 56-pin TSSOP packages
66IN/
3V66-5
66-MHz clock input
66-MHz clock input
66-MHz clock input
66-MHz clock input
66M
66M
66M
66M
Hi-Z
TCLK/4
PCIF/PCI
66IN/2
66IN/2
66IN/2
66IN/2
33 M
33 M
33 M
33 M
Hi-Z
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
TCLK
USB/
DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
Block Diagram
XIN
XOUT
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PWRGD#
PCI_STP#
PLL1
PLL2
PD#
SDATA
SCLK
VDDA
WD
Logic
I2C
Logic
Power
Up Logic
Pin Configuration
REF
VDD 1
XIN 2
XOUT 3
CPUT(0:2)
CPUC(0:2)
VSS 4
PCIF0 5
PCIF1 6
PCIF2 7
VDD 8
VSS 9
3V66_0
PCI0 10
PCI1 11
3V66_1/VCH
PCI2 12
PCI3 13
VDD 14
/2
PCI(0:6)
VSS 15
PCI_F(0:2)
PCI4 16
PCI5 17
48M_USB
PCI6 18
VDD 19
48M_DOT
VSS 20
66B0/3V66_2 21
66B1/3V66_3 22
66B2/3V66_4 23
66IN/3V66_5 24
PD# 25
66B[0:2]/3V66[2:4]
VDDA 26
VSSA 27
66IN/3V66-5
VTT_PWRGD# 28
56 REF
55 S1
54 S0
53 CPU_STP#
52 CPUT0
51 CPUC0
50 VDD
49 CPUT1
48 CPUC1
47 VSS
46 VDD
45 CPUT2
44 CPUC2
43 MULT0
42 IREF
41 VSSIREF
40 S2
39 48M_USB
38 48M_DOT
37 VDD
36 VSS
35 3V66_1/VCH
34 PCI_STP#
33 3V66_0
32 VDD
31 VSS
30 SCLK
29 SDATA
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the devices internal state register.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
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