CY28RS400 Datasheet, PDF (7/18 Pages) Cypress Semiconductor – Clock Generator for ATI RS400 Chipset

CY28RS400
Byte 5: Control Register 5 (continued)
Bit
@Pup
5
0
Name
SRC[T/C]3
4
0
SRC[T/C]2
3
0
SRC[T/C]1
2
0
SRC[T/C]0
1
0
0
0
Byte 6: Control Register 6
Bit
@Pup
7
0
6
0
5
0
4
0
3
HW
2
HW
1
HW
0
HW
Reserved
Reserved
Name
TEST_SEL
TEST_MODE
REF
Reserved
409_410
FS_C
FS_B
FS_A
Byte 7: Vendor ID
Bit
@Pup
7
0
6
0
5
0
4
1
3
1
2
0
1
0
0
0
Name
Description
SRC[T/C]3 CLKREQ#1 control
1 = SRC[T/C]3 stoppable by CLKREQ#1 pin
0 = SRC[T/C]3 free running
SRC[T/C]2 CLKREQ#1 control
1 = SRC[T/C]2 stoppable by CLKREQ#1 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
Reserved
Reserved
Description
REF/N or Tri-state Select
1 = REF/N Clock, 0 = Tri-state
Test Clock Mode Entry Control
1 = REF/N or Tri-state mode, 0 = Normal operation
REF output drive strength.
0 = Low drive, 1 = High drive.
Reserved
409_410 reflects the value of the 409_410 pin sampled on power up. 0 =
409_410 was low during VTT_PWRGD# assertion
FS_C Reflects the value of the FS_C pin sampled on power up. 0 = FS_C
was low during VTT_PWRGD# assertion.
FS_B Reflects the value of the FS_B pin sampled on power up. 0 = FS_B
was low during VTT_PWRGD# assertion.
FS_A Reflects the value of the FS_A pin sampled on power up. 0 = FS_A
was low during VTT_PWRGD# assertion.
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Rev 1.0, November 22, 2006
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