CY28RS400 Datasheet, PDF (1/18 Pages) Cypress Semiconductor – Clock Generator for ATI RS400 Chipset

CY28RS400
Clock Generator for ATI^£ RS400 Chipset
Features
• Supports Intel^£ CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 48 MHz USB clock
• 33 MHz PCI clock
• Low-voltage frequency select input
• I²C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU
SRC
PCI
REF
USB_48
x3
x8
x1
x3
x1
Block Diagram
XIN
XOUT
CPU_STP#
CLKREQ[0:1]#
FS_[C:A]
VTT_PWRGD#
IREF
XTAL
OSC
PLL Ref Freq
PLL1
Divider
Network
PD
PLL2
SDATA
SCLK
I²C
Logic
Pin Configuration
VDD_REF
REF[0:2]
Xin
XOUT
VDD_CPU
CPUT[0:2], CPUC[0:2],
VDD_48
USB_48
VSS_48
VDD_SRC
VTT_PWRGD#/PD
SRCT[0:5],SRCC[0:5]
SCLK
VDD_SRCS
SDATA
SRCST[0:1],SRCSC[0:1]
FSC
VDD_PCI
PCI
CLKREQ#0
CLKREQ#1
SRCT5
SRCC5
VDD_SRC
VDD_48 MHz
VSS_SRC
SRCT4
SRCC4
SRCT3
USB_48
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
SRCST1
SRCSC1
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
56 SSOP/TSSOP
VDD_REF
VSS_REF
REF0/FSA
REF1/FSB
REF2
VDD_PCI
PCI0/409_410
VSS_PCI
CPU_STOP#
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
CPUT2
CPUC2
VDDA
VSSA
IREF
VSS_SRC1
VDD_SRC1
SRCT0
SRCC0
VDD_SRCS
VSS_SRCS
SRCST0
SRCSC0
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 18
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