CY28331 Datasheet, PDF (6/16 Pages) SpectraLinear Inc – Clock Generator for AMD™ Hammer

CY28331
Byte 5: SSCG, Dial-a-Skew™, and Dial-a-Ratio™ Register
Bit
@Pup
Description
7
0
Spread Spectrum Selection:
6
1
bit7 bit6 bit5 % Spread
0
0
0
–1.5
0
0
1
–1.0
0
1
0
–0.7
0
1
1
–0.5 (default)
5
1
1
0
0
±0.75
1
0
1
±0.50
1
1
0
±0.35
1
1
1
±0.25
4
0
HT66 Frequency Fractional Aligner: These bits determine the HT66 fixed frequency when the
3
0
HT66 Output Frequency Selection bit is set. It does not incorporate spread spectrum.
Fract_Align PCI_HT
PCI
2
0
bit[4:0]
(MHz)
(MHz)
1
0
00000
Off
Off
(default)
0
0
00001
00010
66.5
67.5
33.2
33.7
00011
68.5
34.3
00100
69.5
34.8
00101
70.6
35.3
00110
71.6
35.8
00111
72.6
36.3
01000
73.6
36.8
01001
74.7
37.3
01010
75.7
37.8
01011
76.7
38.4
01100
77.7
38.9
01101
78.7
39.4
01110
79.8
39.9
01111
80.8
40.4
10000
81.8
40.9
10001
82.8
41.4
10010
83.9
41.9
10011
84.9
42.4
10100
85.9
43.0
10101
86.9
43.5
10110
88.0
44.0
10111
89.0
44.5
11000
90.0
45.0
11001
91.0
45.5
11010
92.0
46.0
11011
93.1
46.5
11100
94.1
47.0
11101
95.1
47.6
11110
96.1
48.1
11111
97.2
48.6
Byte 6: Watchdog Control Register
Bit @Pup
Name
Description
7
0 HT66 Output Frequency HT66 Output Frequency Selection:
Selection
0: Set according to Frequency Selection Table
1: Set according to Fractional Aligner Table
6
0
Pin 44 Mode Select
Pin 44 Mode Select:
0 = Pin 12 is the output pin as SRESET# signal.
1 = Pin 12 is the input pin which functions as a PD# signal.
Rev 1.0, November 24, 2006
Page 6 of 16