CY28331 Datasheet, PDF (10/16 Pages) SpectraLinear Inc – Clock Generator for AMD™ Hammer

Dial-a-Frequency
CY28331
ROM
Control Register N White
SMBus
Control
Register N
Latch
M Register
Control Register M White
SMBus
Control
Register M
N Register
DAFEN
Figure 2. Dial-a-Frequency Feature
The SMBus controlled Dial-a-Frequency feature is available in
this device via Dial-a-Frequency Control Register N and
Dial-a-Frequency Control Register M. P is a PLL constant that
depends on the frequency selection prior to accessing the
Dial-a-Frequency feature.
Table 5.
FS(3:0)
P
0000
0001
0010
0011
0100
0101
0110
0111
127994667
191992000
191992000
95996000
127994667
191992000
191992000
1000
1001
1010
1011
1100
1101
1110
1111
95966000
95966000
191992000
191992000
191992000
191992000
191992000
191992000
The algorithm is the same for all P values, which is Fcpu =
(P*N)/M with the following conditions. M = (20..58), N =
(21..125) and N > M > N/2.
Operation
Pin strapping on any configuration pin is based on a 10K ohm
resistor connected to either 3.3V (V_DD) or ground (V_SS). When
the V_DD supply goes above 2.0V, the Power-on-Reset circuitry
latches all of the configuration bits into their respective
registers and then allows the outputs to be enabled. The
output may not occur immediately after this time as the PLL
needs to be locked and will not output an invalid frequency.
The CPU frequencies are defined from the hardware-sampled
inputs. Additional frequencies and operating states can be
selected through the SMBus-programmable interface.
Spread spectrum modulation is required for all outputs derived
from the internal CPU PLL2. This include the CPU(0:1),
PCI33(0:6), PCI33_F, and PCI33_HT66(0:3). The REF (0:2),
USB, and 24_48 clocks are not affected by the spread
spectrum modulation. The spread spectrum modulation is set
for both center and down modes using a Lexmark profiles for
amounts of 0.5% and 1.0% at a 33-KHz rate.
The CPU clock driver is of a push-pull type for the differential
outputs, instead of the Athlon open-drain style. The CPU clock
termination has been derived such that a 15-40 ohm, 3.3V
output driver can be used for the CPU clock.
The PCISTOP# signal provides for synchronous control over
the any output, except the PCI33_F, that is running at 33 MHz.
If the PCI33_HT66 outputs are configured to run at 66 MHz will
not be stopped by this signal. The PCISTOP# signal is
sampled by an internal PCI clock such that once it is sensed
low or active, the 33-MHz signals are stopped on the next high
to low transition and remains low.
Rev 1.0, November 24, 2006
Page 10 of 16