CY28RS600 Datasheet, PDF (4/17 Pages) SpectraLinear Inc – Clock Generator for ATI RS5XX, 6XX Chipsets

CY28RS600
Table 3. Block Read and Block Write Protocol (continued)
Block Write Protocol
Bit
Description
.... Data Byte N – 8 bits
.... Acknowledge from slave
.... Stop
Bit
47
55:48
56
....
....
....
Block Read Protocol
Description
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
Description
1
Start
8:2 Slave address–7 bits
9
Write
10 Acknowledge from slave
18:11
19
27:20
28
29
Command Code–8 bits
Acknowledge from slave
Data byte–8 bits
Acknowledge from slave
Stop
Bit
1
8:2
9
10
18:11
19
20
27:21
28
29
37:30
38
39
Byte Read Protocol
Description
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeated start
Slave address–7 bits
Read
Acknowledge from slave
Data from slave–8 bits
NOT Acknowledge
Stop
Control Registers
Byte 0: Output Enable Register 0
Bit
@Pup
7
1
Name
SRC[T/C]7
6
1
SRC[T/C]6
5
1
SRC[T/C]5
4
1
SRC[T/C]4
3
1
SRC[T/C]3
2
1
SRC[T/C]2
1
1
SRC[T/C]1
0
1
SRC [T/C]0
Description
SRC[T/C]7 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Rev 1.0, November 22, 2006
Page 4 of 17