CY28RS600 Datasheet, PDF (1/17 Pages) SpectraLinear Inc – Clock Generator for ATI RS5XX, 6XX Chipsets

CY28RS600
Clock Generator for ATI^£ RS5XX, 6XX Chipsets
Features
• Supports Intel^£ CPU
• Selectable CPU frequencies
• Differential CPU clock pairs (30% over/10%under
clocked)
• 100 MHz differential ATI Graphics clocks (100%
over/10% under clocked)
• 100 MHz differential SRC clocks (10% over/under
clocked)
• 48 MHz USB clock
• I²C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 64-pin TSSOP packages
CPU
x3
SRC
x8
ATIG
X4
REF
x3
USB_48
x2
Block Diagram
XIN
XOUT
CLKREQ# [C:A]
RESET_IN#
FS[C:A]
14.318MHz
Crystal
PLL Reference
CPU
PLL
Divider
SRC
PLL
Divider
SRC
PLL
Divider
VTT_PWRGD#/PD
SDATA
SCLK
Fixed
PLL
Divider
I2C
Logic
Pin Configuration
VDD
REF[0:2]
VDD_CPU
CPUT[0:2]
CPUC[0:2]
VDD_ATIG
ATIGT[0:3]
ATIGC[0:3]
VDD_SRC
SRCT[0:7]
SRCC[0:7]
VDD48
USB48[1:0]
VDD_REF
1
XIN
2
XOUT
3
VDD48
4
USB48_0
5
USB48_1
6
VSS48
7
VTTPWRGD#/PD
8
SCLK
9
SDATA
10
CLKREQA#
11
SRCT7
12
SRCC7
13
VDD_SRC
14
VSS_SRC
15
SRCT6
16
SRCC6
17
SRCT5
18
SRCC5
19
SRCT4_SATAT
20
SRCC4_SATAC
21
VSS_SRC
22
VDD_SRC
23
SRCT3
24
SRCC3
25
SRCT2
26
SRCC2
27
VDD_SRC
28
VSS_SRC
29
SRCT1
30
SRCC1
31
CLKREQB#
32
64 TSSOP
64 VSS_REF
63 FSA_REF0
62 FSB_REF1
61 FSC_REF2
60 RESET_IN#
59 CPU_STOP#
58 CPUT0
57 CPUC0
56 VDD_CPU
55 VSS_CPU
54 CPUT1
53 CPUC1
52 CPUT2
51 CPUC2
50 VDDA
49 VSSA
48 VSSSRC
47 SRCT0
46 SRCC0
45 VSS_SRC
44 VDD_SRC
43 ATIGT0
42 ATIGC0
41 ATIGT1
40 ATIGC1
39 VDD_ATIG
38 VSS_ATIG
37 ATIGT2
36 ATIGC2
35 ATIGT3
34 ATIGC3
33 CLKREQC#
Rev 1.0, November 22, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 17
www.SpectraLinear.com