CY2SSTV857-32 Datasheet, PDF (2/8 Pages) SpectraLinear Inc – Differential Clock Buffer/Driver DDR400/PC3200-Compliant

40 QFN Package
CY2SSTV857-32
VSS
Y2#
Y2
VDDQ
CLK
CLK#
VDDQ
AVDD
AVSS
VSS
40
1
39
38
37 36
35
34
33
32
31 ₃₀
2
29
3
28
4
40 QFN
27
5
CY2SSTV857-32
26
6
25
7
24
8
23
9
22
10 _{11 12 13 14 15 16 17 18 19 20} 21
Y7#
Y7
VDDQ
PD#
FBIN
FBIN#
VDDQ
VDDQ
FBOUT#
FBOUT
Pin Description
Pin #
48 TSSOP
Pin #
40 QFN
Pin Name I/O^[1]
Pin Description
Electrical
Characteristics
13, 14
5,6
CLK, CLK# I Differential Clock Input.
LV Differential Input
35
25
FBIN#
I Feedback Clock Input. Connect to FBOUT# for Differential Input
accessing the PLL.
36
26
FBIN
I Feedback Clock Input. Connect to FBOUT for
accessing the PLL.
3, 5, 10, 20, 22 37,39,3,12,14
Y(0:4)
O Clock Outputs.
Differential Outputs
2, 6, 9, 19, 23 36,40,2,11,15
Y#(0:4)
O Clock Outputs.
27, 29, 39, 44, 46 17,19,29,32,34
Y(9:5)
O Clock Outputs.
Differential Outputs
26, 30, 40, 43, 47 16,20,30,31,35 Y#(9:5)
O Clock Outputs.
32
21
FBOUT
O Feedback Clock Output. Connect to FBIN for Differential Outputs
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
33
22
FBOUT#
O Feedback Clock Output. Connect to FBIN# for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
37
27
PD#
I Power Down Input. When PD# is set HIGH, all
Q and Q# outputs are enabled and switch at the
same frequency as CLK. When set LOW, all Q
and Q# outputs are disabled Hi-Z and the PLL
is powered down.
4, 11,12,15, 21, 4,7,13,18,23,24,
28, 34, 38, 45 28,33,38
VDDQ
2.6V Power Supply for Output Clock Buffers. 2.6V Nominal
16
8
AVDD
2.6V Power Supply for PLL. When VDDA is at 2.6V Nominal
GND, PLL is bypassed and CLK is buffered
directly to the device outputs. During disable
(PD# = 0), the PLL is powered down.
1, 7, 8, 18, 24, 25, 1,10
31, 41, 42, 48
VSS
Common Ground.
0.0V Ground
17
9
AVSS
Analog Ground.
0.0V Analog
Ground
Note:
1. A bypass capacitor (0.1PF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
Rev 1.0, November 21, 2006
Page 2 of 8