CY2SSTV857-32 Datasheet, PDF (1/8 Pages) SpectraLinear Inc – Differential Clock Buffer/Driver DDR400/PC3200-Compliant

CY2SSTV857-32
Differential Clock Buffer/Driver DDR400/PC3200-Compliant
Features
• Operating frequency: 60 MHz to 230 MHz
• Supports 400 MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of –40°C to 85°C
• Conforms to JEDEC DDR specification
Description
The CY2SSTV857-32 is a high-performance, low-skew,
low-jitter zero-delay buffer designed to distribute differential
clocks in high-speed applications. The CY2SSTV857-32
generates ten differential pair clock outputs from one differ-
ential pair clock input. In addition, the CY2SSTV857-32
features differential feedback clock outpts and inputs. This
allows the CY2SSTV857-32 to be used as a zero delay buffer.
When used as a zero delay buffer in nested clock trees, the
CY2SSTV857-32 locks onto the input reference and translates
with near-zero delay to low-skew outputs.
Block Diagram
PD ³⁷
AVDD ¹⁶
Test and
Powerdown
Logic
CLK ¹³
CLK# ¹⁴
PLL
FBIN ³⁶
FBIN# ³⁵
Pin Configuration
3
2
Y0
Y0#
5 _Y1
6 _Y1#
10 _Y2
9 _Y2#
20 _Y3
19 _Y3#
22 _Y4
23 _Y4#
46 _Y5
47 _Y5#
44 _Y6
43 _Y6#
39 _Y7
40 _Y7#
29 _Y8
30 _Y8#
27 _Y9
26 _Y9#
32 _FBOUT
33 _FBOUT#
VSS
1
Y0#
2
Y0
3
VDDQ
4
Y1
5
Y1#
6
VSS
7
VSS
8
Y2#
9
Y2
10
VDDQ
11
VDDQ
12
CLK
13
CLK#
14
VDDQ
15
AVDD
16
AVSS
17
VSS
18
Y3#
19
Y3
20
VDDQ
21
Y4
22
Y4#
23
VSS
24
48
VSS
47
Y5#
46
Y5
45
VDDQ
44
Y6
43
Y6#
42
VSS
41
VSS
40
Y7#
39
Y7
38
VDDQ
37
PD#
36
FB IN
35
FB IN #
34
VDDQ
33
FBOUT#
32
FBOUT
31
VSS
30
Y8#
29
Y8
28
VDDQ
27
Y9
26
Y9#
25
VSS
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 8
www.SpectraLinear.com