CY28405 Datasheet, PDF (17/18 Pages) Cypress Semiconductor – CK409-Compliant Clock Synthesizer

CY28405
Table 9. Maximum Lumped Capacitive Output Loads
Clock
PCI Clocks
3V66 Clocks
Max Load
30
30
Units
pF
pF
USB Clock
20
pF
DOT Clock
10
pF
REF Clock
30
pF
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
CPUT
:
T_PCB
:
:
CPUC
IR E F
:
T_PCB
:
M easurem ent
P oint
2pF
M easurem ent
P oint
2pF
Figure 7. 0.7V Load Configuration
O utput under T est
P ro b e
Load Cap
3.3V sig n als
tD C
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0V
Tr
Tf
Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameter Measurement)
Table 10.CPU Clock Current Select Function
Board Target Trace/Term Z
50 Ohms
Reference R, I_REF – V_DD (3*R_REF)
R_REF = 475 1%, I_REF = 2.32 mA
Output Current
I_OH = 6*I_REF
V_OH @ Z
0.7V @ 50
Rev 1.0, November 20, 2006
Page 17 of 18