CY28405-3 Datasheet, PDF (14/16 Pages) SpectraLinear Inc – Clock Synthesizer with Differential SRC and CPU Outputs

CY28405-3
AC Electrical Specifications (continued)
Parameter
Description
T_CCJ
REF Cycle to Cycle Jitter
T_SKEW
Any REF to REF clock skew
ENABLE/DISABLE and SET-UP
T_STABLE
Clock Stabilization from Power-up
T_SS
Stopclock Set-up Time
T_SH
Stopclock Hold Time
Table 7. Group Timing Relationship and Tolerances
Condition
Measurement at 1.5V
Measurement @1.5V
Group
3V66 to PCI
Conditions
3V66 Leads PCI
Table 8. USB to DOT Phase Offset
Parameter
DOT Skew
USB Skew
VCH SKew
Typical
0°
180°
0°
Value
0.0ns
0.0ns
0.0ns
Tolerance
1000 ps
1000 ps
1000 ps
Test and Measurement Set-up
Table 9. Maximum Lumped Capacitive Output Loads
Clock
PCI Clocks
Max Load
30
Units
pF
3V66 Clocks
30
pF
USB Clock
20
pF
DOT Clock
10
pF
REF Clock
30
pF
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Min.
Max.
Unit
–
1000
ps
–
500
ps
–
1.8
ms
10.0
–
ns
0
–
ns
Min.
1.5ns
Offset
Max.
3.5ns
CPUT
:
T_PCB
:
M easurem ent
P oint
2pF
:
CPUC
IR E F
:
T_PCB
:
M easurem ent
P oint
2pF
Figure 7. 0.7V Load Configuration
Rev 1.0, November 22, 2006
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