CY28339 Datasheet, PDF (10/17 Pages) SpectraLinear Inc – Intel CK408 Mobile Clock Synthesizer

CY28339
t _setup
PCI_STP#
PCIF
PCI
VID (0:3),
SEL (0,1)
VTT_PWRGD#
PWRGD
Figure 8. PCI_STOP# Deassertion Waveform
VDD Clock Gen
Clock State State 0
0.2-0.3mS
Delay
State 1
Wait for _{Sample Sels}
VTT_PWRGD#
State 2
Device is not affected,
VTT_PWRGD# is ignored.
State 3
Off
Clock Outputs
Off
Clock VCO
VDDA = 2.0V
S0
Power Off
On
On
Figure 9. VTT_PWRGD# Timing Diagram
S1
Delay
>0.25mS
VTT_PWRGD# = Low
S2
Sample
Inputs straps
VDD3.3= off
S3
Normal
Operation
Wait for <1.8ms
Enable Outputs
VTT_PWRGD# = toggle
Figure 10. Clock Generator Power-up/Run State Program
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is ±7% as shown in
the current accuracy table.
Rev 1.0, November 25, 2006
Page 10 of 17