CY28339 Datasheet, PDF (1/17 Pages) SpectraLinear Inc – Intel CK408 Mobile Clock Synthesizer

CY28339
Intel^£ CK408 Mobile Clock Synthesizer
Features
• Compliant with Intel^® CK 408 rev 1.1 Mobile Clock
Synthesizer specifications
• 3.3V power supply
• Two differential CPU clocks
• Nine copies of PCI clocks
• Three copies configurable PCI free-running clocks
• Two 48 MHz clocks (USB, DOT)
• Five/six copies of 3V66 clocks
Table 1. Frequency Table^[1]
S2 S1 CPU (1:2) 3V66
10
100M
66M
11
133M
66M
00
100M
66M
01
133M
66M
M 0 TCLK/2 TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66M
66M
TCLK/4
• One VCH clock
• One reference clock at 14.318 MHz
• SMBus support with read-back capabilities
• Ideal Lexmark profile Spread Spectrum electromag-
netic interference (EMI) reduction
• Dial-a-Frequency™ features
• Dial-a-dB™ features
• 48-pin TSSOP package
66IN/3V66–5
66-MHz clock input
66-MHZ clock input
66M
66M
TCLK/4
PCIF, PCI
66IN/2
66IN/2
33 M
33 M
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
TCLK
USB/ DOT
48M
48M
48M
48M
TCLK/2
Block Diagram
X1
XTAL
X2
OSC
PWR
PLL Ref Freq
PLL 1
S1:2
VTT_PWRGD##
CPU_STOP#
Gate
Divider
Network
PWR
Stop
Clock
Control
PWR
Stop
Clock
Control
PCI_STOP#
PD#
/2
PWR
PWR
PLL 2
PWR
SDATA
SCLK
SMBus
Logic
VDD_REF
REF
VDD_CPU
CPUT1:2
CPUC1:2
VDD_PCI
PCIF
PCI0:2
PCI4:8
VDD_3V66
3V66_0:1
3V66_2:4/
66BUFF0:2
3V66_5/ 66IN
VDD_48MHz
USB (48MHz)
DOT (48MHz)
VCH_CLK/ 3V66_1
Pin Configuration
XIN
XOUT
GND_REF
PCI7
PCI8
PCIF
GND_PCI
PCI0
PCI1
PCI2
VDD_PCI
PCI4
PCI5
PCI6
VDD_3V66
GND_3V66
66BUFF0/3V66_2
66BUFF1/3V66_3
66BUFF2/3V66_4
66IN/3V66_5
PD#
VDD_CORE
GND_CORE
VTT_PWRGD#
Top View
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
VDD_REF
REF
S1
CPU_STOP#
VDD_CPU
CPUT1
CPUC1
GND_CPU
VDD_CPU
CPUT2
CPUC2
IREF
S2
USB_48MHz
DOT_48MHz
VDD_48 MHz
GND_48 MHz
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_3V66
GND_3V66
SCLK
SDATA
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device’s internal state register.
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
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