CY2SSTU32866 Datasheet, PDF (1/24 Pages) SpectraLinear Inc – 1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity

CY2SSTU32866
1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant
Data Register with Parity
Features
• Operating frequency: DC to 500 MHz
• Supports DDRII SDRAM
• Two operations modes: 25 bit (1:1) and 14 bit (1:2)
• 1.8V operation
• Fully JEDEC-compliant (JESD 82-10)
• 96-ball FBGA
Functional Description
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to
drive the DDR-II DIMM load. The CY2SSTU32866 operates
from a differential clock (CK and CK#). Data are registered at
the crossing of CK going high, and CK# going LOW.
The C0 input controls the pinout configuration of the 1:2 pinout
from A configuration (when LOW) to B configuration (when
HIGH). The C1 input controls the pinout configuration from
25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH).
The device monitors both DCS# and CSR# inputs and will gate
the Qn outputs from changing states when both DCS# and
CSR# inputs are HIGH. If either DCS# or CSR# input is LOW,
the Qn outputs will function normally. The RESET# input has
priority over the DCS# and CSR# control and will force the
outputs LOW. If the DCS#-control functionality is not desired,
the CSR# input can be hardwired to ground, in which case the
set-up time requirement for DCS# would be the same as for
the other D data inputs.
The device supports low-power standby operation. When the
reset input (RESET#) is LOW, the differential input receivers
are disabled, and undriven (floating) data, clock, and reference
voltage (VREF) inputs are allowed. In addition, when RESET#
is LOW, all registers are reset and all outputs are forced LOW.
The LVCMOS RESET# and Cn inputs must always be held at
a valid logic HIGH or LOW level. To ensure defined outputs
from the register before a stable clock has been supplied,
RESET# must be held in the LOW state during power-up.
In the DDR-II RDIMM application, RESET# is specified to be
completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven low quickly, relative to the time to
disable the differential input receivers. However, when coming
out of reset, the register will become active quickly, relative to
the time to enable the differential input receivers.
Pin Configuration
1
2
3
4
5
6
A
DCKE PPO VREF VDD QCKE NC
B
D2 D15 GND GND Q2 Q15
C
D3 D16 VDD VDD Q3 Q16
D
DODT QERR# GND GND QODT NC
E
D5 D17 VDD VDD Q5 Q17
F
D6 D18 GND GND Q6 Q18
G
PAR_IN RST# VDD VDD C1 C0
H
CK DCS# GND GND QCS# NC
J
CK# CSR# VDD VDD ZOH ZOL
K
D8 D19 GND GND Q8 Q19
L
D9 D20 VDD VDD Q9 Q20
M D10 D21 GND GND Q10 Q21
N
D11 D22 VDD VDD Q11 Q22
P
D12 D23 GND GND Q12 Q23
R
D13 D24 VDD VDD Q13 Q24
T
D14 D25 VREF VDD Q14 Q25
1
2
3
4
5
6
1:1 Register C0 = 0, C1=0
1
2
3
4
5
6
A
DCKE PPO VREF VDD QCKEA QCKEB
B
D2 NC GND GND Q2A Q2B
C
D3 NC VDD VDD Q3A Q3B
D
DODT QERR# GND GND QODTA QODTB
E
D5 NC VDD VDD Q5A Q5B
F
D6 NC GND GND Q6A Q6B
G
PAR_IN RST# VDD VDD C1 C0
H
CK DCS# GND GND QCSA# QCSB#
J
CK# CSR# VDD VDD ZOH ZOL
K
D8 NC GND GND Q8A Q8B
L
D9 NC VDD VDD Q9A Q9B
M D10 NC GND GND Q10A Q10B
N
D11 NC VDD VDD Q11A Q11B
P
D12 NC GND GND Q12A Q12B
R
D13 NC VDD VDD Q13A Q13B
T
D14 NC VREF VDD Q14A Q14B
1
2
3
4
5
6
1:2 Register A C0 = 0, C1=1
1
2
3
4
5
6
A
D1 PPO VREF VDD Q1A Q1B
B
D2 NC GND GND Q2A Q2B
C
D3 NC VDD VDD Q3A Q3B
D
D4 QERR# GND GND Q4A Q4B
E
D5 NC VDD VDD Q5A Q5B
F
D6 NC GND GND Q6A Q6B
G
PAR_IN RST# VDD VDD C1 C0
H
CK DCS# GND GND QCSA# QCSB#
J
CK# CSR# VDD VDD ZOH ZOL
K
D8 NC GND GND Q8A Q8B
L
D9 NC VDD VDD Q9A Q9B
M D10 NC GND GND Q10A Q10B
N
DODT NC VDD VDD QODTA QODTB
P
D12 NC GND GND Q12A Q12B
R
D13 NC VDD VDD Q13A Q13B
T
DCKE NC VREF VDD QCKEA QCKEB
1
2
3
4
5
6
1:2 Register B C0 = 1, C1=1
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
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