CY28412 Datasheet, PDF (1/16 Pages) SpectraLinear Inc – Clock Generator for Intel® Grantsdale Chipset

PRELIMINARY
CY28412
Clock Generator for Intel^® Grantsdale Chipset
Features
• Supports Intel^£ P4 and Prescott CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
• Low-voltage frequency select input
• I²C Support with read back capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP package
CPU SRC
PCI
x2 / x3 x7 / x8 x 8
REF
x2
DOT96 USB_48
x1
x1
Block Diagram
XIN
XOUT
CPU_STP#
PCI_STP#
FS_[C:A]
VTT_PWRGD#
IREF
XTAL
OSC
PLL Ref Freq
PLL1
Divider
Network
PD
PLL2
SDATA
SCLK
I²C
Logic
Pin Configuration
VDD_REF
REF[1:0]
PCI0
PCI1
VDD_CPU
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
VDD_SRC
SRCT[0:6], SRCC[0:6],
SATA[T/C]
VDD_PCI
GND_PCI
PCI2
PCI3
PCI4
PCI5
GND_PCI
VDD_PCI
PCI[0:5]
VDD_PCI
TEST_SEL/PCIF0
VDD_PCIF
ITP_EN/PCIF1
PCIF[0:1]
VDD_48
USB48/FS_B
VDD_48 MHz
GND_48
DOT96T
DOT96T
DOT96C
USB_48
DOT96C
VTT_PwrGd#/PD
SRCT0
SRCC0
SRCT1
STCC1
VDD_SRC
GND_SRC
SRCT2
SRCC2
SATAT
SATAC
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
56 SSOP
VDD_REF
REF0/FS_C
REF1/FS_A
GND_REF
X1
X2
SDATA
SCLK
GND_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
GND_A
VDD_A
CPUT2_ITP/SRCT6
CPUC2_ITP/SRCC6
VDD_SRC
SRCT5
SRCC5
GND_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VDD_SRC
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
Page 1 of 16
www.SpectraLinear.com