CY28301 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – Frequency Generator for Intel Integrated Chipset

CY28301
Frequency Generator for Intel(r) Integrated Chipset
Features
• Single chip FTG solution for Intel^® Solano/810E/810
• Support SMBus byte Read/Write and block Read/Write
operations to simplify system BIOS development
• Vendor ID and revision ID support
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Two copies of CPU clock
• Thirteen copies of SDRAM clock
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Three copies of 66 MHz outputs
• Two copies of 48 MHz outputs
• One copy of 14.31818 MHz reference clock
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48 MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps
CPU, 3V66 Output Skew:............................................ 175 ps
SDRAM, APIC, 48-MHz Output Skew:........................ 250 ps
PCI Output Skew:........................................................ 500 ps
CPU to SDRAM Skew (@ 133 MHz) ......................... ±0.5 ns
CPU to SDRAM Skew (@ 100 MHz)..................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz) ........................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead)...........................1.5 to 3.5 ns
PCI to APIC Skew ...................................................... ±0.5 ns
Block Diagram
Pin Configuration^[1]
X1
X2
SDATA
SCLK
(FS0:4)
XTAL
OSC
PLL REF FREQ
SMBus
Logic
Divider,
Delay, and
Phase
Control
Logic
PLL 1
PD#
PLL2
/2
VDD_REF
REF/FS1
VDD_CPU
CPU0:1
2
VDD_APIC
APIC
VDD_3V66
3V66_0:2
3
VDD_PCI
PCI0
PCI1
PCI2/SEL24_48MHz#*
5 ^PCI3:7
VDD_SDRAM
SDRAM0:11,
13 _{SDRAM_F}
VDD_48MHz
48MHz/FS0
24_48MHz
VDD_REF 1
X1 2
X2 3
GND_REF 4
GND_3V66 5
3V66_0 6
3V66_1 7
3V66_2 8
VDD_3V66 9
VDD_PCI 10
PCI0 11
PCI1 12
PCI2/SEL24_48MHz#* 13
GND_PCI 14
PCI3 15
PCI4 16
PCI5 17
VDD_PCI 18
PCI6 19
PCI7 20
GND_PCI 21
PD#* 22
SCLK 23
SDATA 24
VDD_SDRAM 25
SDRAM11 26
SDRAM10 ²⁷
GND_SDRAM 28
56 REF/FS1*
55 VDD_APIC
54 APIC
53 VDD_CPU
52 CPU0
51 CPU1
50 GND_CPU
49 GND_SDRAM
48 SDRAM0
47 SDRAM1
46 SDRAM2
45 VDD_SDRAM
44 SDRAM3
43 SDRAM4
42 SDRAM5
41 GND_SDRAM
40 SDRAM6
39 SDRAM7
38 SDRAM_F
37 VDD_SDRAM
36 GND_48MHz
35 24_48MHz
34 48MHz/FS0*
33 VDD_48MHz
32 VDD_SDRAM
31 SDRAM8
30 SDRAM9
29 GND_SDRAM
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design
should not rely solely on internal pull-up resistor to set I/O pins HIGH.
Rev 1.0, November 27, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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