CY28159 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – Clock Generator for Serverworks Grand Champion Chipset Applications

CY28159
Clock Generator for Serverworks Grand Champion Chipset
Applications
1CY28159
Features
• Eight differential CPU clock outputs
• One PCI output
• One 14.31818 MHz reference clock
• Two 48 MHz clocks
• All outputs compliant with Intel^® specifications
• External resistor for current reference
• Selection logic for differential swing control, test mode,
Hi-Z, power-down and spread spectrum
• 48-pin SSOP and TSSOP packages
Table 1. Frequency Selection
SEL 100/133 S0
S1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CPU(0:7), CPU#(0:7)
100 MHz
100 MHz
100 MHz
Hi-Z
133.3MHz
133.3MHz
200MHz
N/A
3V33
33.3MHz
33.3MHz
Disable
Hi-Z
33.3MHz
33.3MHz
33.3MHz
N/A
48M(0,1)
48 MHz
Disable
Disable
Hi-Z
48 MHz
Disable
48 MHz
N/A
Notes
Normal Operation
Test Mode(recommended)
Test Mode (optional)
Hi-Z all outputs
Optional
Optional
o7ptional
Reserved
Table 2.
Block Diagram
XIN
XOUT
OSC
MultSel(0:1)
I_Ref
SSCG#
SEL100/133
VCO
I
Control
REF
VDDI
VSSI
CPU (0:7)
CPU (0:7)#
48M(0,1)/S(0,1)
PD#
S(0,1)
VDDL
3V33
VSSL
Pin Configuration
3V33 1
VDD 2
48M0/S0 3
48M1/S1 4
VSS 5
VDD 6
CPU0 7
CPU0# 8
VSS 9
CPU1 10
CPU1# 11
VDD 12
CPU2 13
CPU2# 14
VSS 15
CPU3 16
CPU3# 17
VDD 18
REF 19
SSCG# 20
VSS 21
XIN 22
XOUT 23
VDD 24
48
SEL100/133
47
VSS
46
VDDA
45
VSSA
44
PD#
43
VDD
42
CPU4
41
CPU4#
40
VSS
39
CPU5
38
CPU5#
37
VDD
36
CPU6
35
CPU6#
34
VSS
33
CPU7
32
CPU7#
31
VDD
30
MULT0
29
MULT1
28
VSS
27
VSSA
26
IREF
25
VDDA
Rev 1.0, November 24, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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