S25FL127S Datasheet, PDF (91/131 Pages) SPANSION – 128 Mbit (16 Mbyte) MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core

Data Sheet (Preliminary)
CS#
SCLK
IO0
Figure 10.28 Quad Output Read (QOR 6Bh or 4QOR 6Ch) Command Sequence without Read Latency
012345678
38 39 40 41 42 43 44 45 46 47 48 49 50 51
Instruction
32 Bit Address
7 6 5 4 3 2 1 0 31
10
8 Dummy Cycles
Data 1
40
Data 2
40
IO1
5151
IO2
6262
IO3
Notes:
1. A = MSB of address = A23 for ExtAdd = 0, or A31 for ExtAdd = 1 or command 6Ch.
2. LC = 11b shown.
7373
10.4.5
Dual I/O Read (DIOR BBh or 4DIOR BCh)
The instruction
 BBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 BBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 BCh is followed by a 4-byte address (A31-A0)
The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar
to the Dual Output Read command but takes input of the address two bits per SCK rising edge. In some
applications, the reduced address input time might allow for code execution in place (XIP) i.e. directly from
the memory device.
The maximum operating clock frequency for Dual I/O Read is 108 MHz.
For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and
SO before data begins shifting out of IO0 and IO1.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the
initial address. During the dummy cycles, the data value on SI and SO are “don’t care” and may be high
impedance. The number of dummy cycles is determined by the frequency of SCK (Table 8.7, Latency Codes
on page 58). The number of dummy cycles is set by the LC bits in the Configuration Register (CR1).
The Latency Code table provides cycles for mode bits so a series of Dual I/O Read commands may eliminate
the 8-bit instruction after the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the
following command will also be a Dual I/O Read command. The first Dual I/O Read command in a series
starts with the 8-bit instruction, followed by address, followed by four cycles of mode bits, followed by a
latency period. If the mode bit pattern is Axh the next command is assumed to be an additional Dual I/O Read
command that does not provide instruction bits. That command starts with address, followed by mode bits,
followed by latency.
The enhanced high performance feature removes the need for the instruction sequence and greatly improves
code execution (XIP). The upper nibble (bits 7-4) of the Mode bits control the length of the next Dual I/O Read
command through the inclusion or exclusion of the first byte instruction code. The lower nibble (bits 3-0) of the
Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits equal Axh, then the device
remains in Dual I/O enhanced high performance Read Mode and the next address can be entered (after CS#
is raised high and then asserted low) without the BBh or BCh instruction, as shown in Figure 10.32; thus,
eliminating eight cycles for the command sequence. The following sequences will release the device from
Dual I/O enhanced high performance Read mode; after which, the device can accept standard SPI
commands:
1. During the Dual I/O enhanced high performance Command Sequence, if the Mode bits are any
value other than Axh, then the next time CS# is raised high the device will be released from Dual
I/O Read enhanced high performance Read mode.
2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input
(IO0 and IO1) are not set for a valid instruction sequence, then the device will be released from
Dual I/O enhanced high performance Read mode. Note that the four mode bit cycles are part of the
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