S25FL127S Datasheet, PDF (89/131 Pages) SPANSION – 128 Mbit (16 Mbyte) MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core

Data Sheet (Preliminary)
10.4.3
Dual Output Read (DOR 3Bh or 4DOR 3Ch)
The instruction
 3Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
 3Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
 3Ch is followed by a 4-byte address (A31-A0)
Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1
(SO). Two bits are shifted out at the SCK frequency by the falling edge of the SCK signal.
The maximum operating clock frequency for the Dual Output Read command is 108 MHz. For Dual Output
Read commands, there are zero or eight dummy cycles required after the last address bit is shifted into SI
before data begins shifting out of IO0 and IO1. This latency period (i.e., dummy cycles) allows the device’s
internal circuitry enough time to read from the initial address. During the dummy cycles, the data value on SI
is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the frequency of
SCK (refer to Table 8.7, Latency Codes on page 58).
The address can start at any byte location of the memory array. The address is automatically incremented to
the next higher address in sequential order after each byte of data is shifted out. The entire memory can
therefore be read out with one single read instruction and address 000000h provided. When the highest
address is reached, the address counter will wrap around and roll back to 000000h, allowing the read
sequence to be continued indefinitely.
Figure 10.24 Dual Output Read Command Sequence (3-Byte Address, 3Bh [ExtAdd=0], LC=10b)
CS#
SCK
IO0
IO1
Phase
7 6 5 4 3 2 1 0 23 22 21 0
Instruction
Address
8 Dummy Cycles
64 2064 20
75 3175 31
Data 1
Data 2
Figure 10.25 Dual Output Read Command Sequence
(4-Byte Address, 3Ch or 3Bh [ExtAdd=1, LC=10b])
CS#
SCK
IO0
IO1
Phase
7 6 5 4 3 2 1 0 31 30 29 0
Instruction
Address
8 Dummy Cycles
64 2064 20
75 3175 31
Data 1
Data 2
April 25, 2013 S25FL127S_00_02
S25FL127S
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