S29WS-P_07 Datasheet, PDF (83/94 Pages) SPANSION – MirrorBit® Flash Family 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory

Data Sheet
CR1.0
CR0.13
CR0.12
CR0.11
Table 11.7 Example of Programmable Wait States
Programmable
Wait State
0000 = initial data is valid on the 2rd rising CLK edge after addresses are latched
0001 =initial data is valid on the 3rd rising CLK edge after addresses are latched
0010 = initial data is valid on the 4th rising CLK edge after addresses are latched
0011 = initial data is valid on the 5th rising CLK edge after addresses are latched
0100 = initial data is valid on the 6th rising CLK edge after addresses are latched
0101 = initial data is valid on the 7th rising CLK edge after addresses are latched
0110 = Reserved
0111 = Reserved
1000 = initial data is valid on the 8th rising CLK edge after addresses are latched
1001 = initial data is valid on the 9th rising CLK edge after addresses are latched
101 1= initial data is valid on the 10th rising CLK edge after addresses are latched
.
.
1101 = Reserved
1110 = Reserved
1111 = Reserved
Figure 11.25 Back-to-Back Read/Write Cycle Timings
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank
t_WC
t_RC
t_RC
Begin another
write or program
command sequence
t_WC
CE#
OE#
WE#
Data
t_WPH
t_OE
t_OEH
t_WP
t_DS
PD/30h
t_ACC
t_DH
t_OEZ
t_OEH
RD
t_GHWL
RD
AAh
Addresses
PA/SA
t_AS
t_SR/W
RA
RA
555h
AVD#
t_AH
Note:
Breakpoints in waveforms indicate that system may alternately read array data from the non-busy bank while checking the status of the
program or erase operation in the busy bank. The system should read status twice to ensure valid information.
September 28, 2007 S29WS-P_00_A11
S29WS-P
83