S29WS-P_07 Datasheet, PDF (10/94 Pages) SPANSION – MirrorBit® Flash Family 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory

Data Sheet
2. Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Table 2.1 Input/Output Descriptions
Symbol
A_MAX–A0
DQ15–DQ0
CE#
OE#
WE#
V_CC
V_CCQ
V_SS
NC
RDY
CLK
AVD#
RESET#
WP#
ACC
RFU
Type
Input
I/O
Input
Input
Input
Supply
Supply
Supply
No Connect
Output
Input
Input
Input
Input
Input
Reserved
Description
Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for WS256P, and
22 for WS128P)
Data input/output.
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
Device Power Supply
Device Input/Output Power Supply (Must be ramped simultaneously with V_CC)
Ground.
Not connected internally.
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter. Should be at V_IL or V_IH while in asynchronous mode.
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode, causes
starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At V_IL, disables program and erase functions in the four outermost sectors. Should be at
V_IH for all other conditions.
Acceleration Input. At V_HH, accelerates programming; automatically places device in unlock bypass
mode. At V_IL, disables all program and erase functions. Should be at V_IH for all other conditions.
Reserved for future use (see MCP look-ahead pinout for use with MCP).
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S29WS-P
S29WS-P_00_A11 September 28, 2007