S29PL-N Datasheet, PDF (80/85 Pages) SPANSION – 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory

Preliminary
13 Commonly Used Terms
Term
ACC
A_max
A_min
Asynchronous
Autoselect
Bank
Boot sector
Boundary
Burst Read
Byte
CFI
Clear
Configuration Register
Continuous Read
Erase
Erase Suspend/Erase Resume
BGA
Linear Read
MCP
Memory Array
MirrorBit™ Technology
Page
Definition
ACCelerate. A special purpose input signal which allows for faster programming or
erase operation when raised to a specified voltage above V_CC. In some devices ACC
may protect all sectors when at a low voltage.
Most significant bit of the address input [A23 for 256 Mbit, A22 for 128 Mbit, A21 for
64 Mbit]
Least significant bit of the address input signals (A0 for all devices in this document).
Operation where signal relationships are based only on propagation delays and are
unrelated to synchronous control (clock) signal.
Read mode for obtaining manufacturer and device information as well as sector
protection status.
Section of the memory array consisting of multiple consecutive sectors. A read
operation in one bank, can be independent of a program or erase operation in a
different bank for devices that offer simultaneous read and write feature.
Smaller size sectors located at the top and or bottom of Flash device address space.
The smaller sector size allows for finer granularity control of erase and protection for
code or parameters used to initiate system operation after power on or reset.
Location at the beginning or end of series of memory locations.
See synchronous read.
8 bits
Common Flash Interface. A Flash memory industry standard specification [JEDEC 137-
A and JESD68.01] designed to allow a system to interrogate the Flash to determine its
size, type and other performance parameters.
Zero (Logic Low Level)
Special purpose register which must be programmed to enable synchronous read
mode
Synchronous method of burst read whereby the device reads continuously until it is
stopped by the host, or it has reached the highest address of the memory array, after
which the read address wraps around to the lowest memory array address
Returns bits of a Flash memory array to their default state of a logical One (High Level).
Halts an erase operation to allow reading or programming in any sector that is not
selected for erasure
Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array
and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram
for further details.
Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with
or without wraparound before requiring a new initial address.
Multi-Chip Product. A method of combining integrated circuits in a single package by
stacking multiple die of the same or different devices.
The programmable area of the product available for data storage.
Spansion™ trademarked technology for storing multiple bits of data in the same
transistor.
Group of words that may be accessed more rapidly as a group than if the words were
accessed individually.
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S29PL-N MirrorBit™ Flash Family
S29PL-N_00_A4 November 23, 2005